TMPM330 - Keil

13.3 Conversion Clock
ADCLK
fc
Under development
● The conversion time is calculated by the 46 conversion clock.
Fig. 13-14 A/D Conversion Clock Setting Register
TMPM330 (rev 0.4) 13-15
TMPM330
Example: If fsys = fc = 32 MHz/ 54MHz
Prescaler [ADDCLK2:0] tconv.(conversion time) tconv.(conversion time)
40MHz
32MHz
1 1.15μs 1.44μs
1/2 2.3μs 2.88μs
1/4 4.6μs 5.75μs
Variable S/H time
Conversion
clock
40MHz
A/D Conversion Clock Setting Register
7 6 5 4 3 2 1 0
Bit symbol TSH3 tSH2 tSH1 tSH0 ADCLK2 ADCLK1 ADCLK0
Read/Write R/W R/W R/W R/W R R/W R/W R/W
After reset 1 0 0 0 0 0 0 0
Select the A/D sample hold time
"0" is read. Select the A/D prescaler output
1000: 8 conversion clock 1001: 16 conversion clock
1010: 24 conversion clock 1011: 32 conversion clock
0011: 64 conversion clock
000: fc
001: fc/2
Function 1100: 128 conversion clock 1101: 512 conversion clock
010: fc/4
The setup other than those above: reserved
011: fc/8
100: fc/16
111:reserved
÷1 ÷2 ÷4 ÷8 ÷16
ADDCLK2:0
S/H time 40MHz tconv.(conversion time)
Conversion clk*8 (0.2 μs) 1.15μs
Conversion clk*16 (0.4 μs) 1.35μs
Conversion clk*24 (0.6 μs) 1.55μs
Conversion clk*32 (0.8 μs) 1.75μs
Conversion clk*64 (1.6 μs) 2.55μs
Conversion clk*128 (3.2 μs) 4.15μs
Conversion clk*512 (12.8 μs) 13.75μs
(Note) Please do not change the analog to digital conversion clock setting during the
analog to digital translation.
Fig. 13-15 A/D Conversion Time
ADCLK
Analog/ Digital Converter