TMPM330 - Keil

11.3.2.2 Preconfiguration
Under development
TMPM330 (rev0.4)11-30
TMPM330
Before transmitting data, transmission settings to the Transmit Control Register and
the transmit buffer are required.
(1) Wait Time for Bus to be Free
Configure the wait time for a bus to be free with the CECTCR bit. It can be specified
for each bit cycle from 1 to 16.
Start point to check if a bus is free is the end of final bit. If a bus is free for specified bit cycles of “1”,
transmission starts.
(2) Transmitting Broadcast Message
Set the CECTCR bit when transmitting a broadcast message. If this bit is set, “0”
response during an ACK cycle results in an error. If not, “1” response during an ACK cycle results in
an error.
(3) Adjusting Transmission Waveform
Final bit Check if bus is free Beginning of
transmission
Both start bit and data bit are capable of adjusting the rising timing and cycle. With the CECTCR
bits, the timing can be specified between
the defined fastest rising/cycle timing and the reference value.
The following figures show how the waveforms differ according to the configurations of the start bit,
logical “0” and logical “1”.
(Reference) The configuration of is applied for waveform of an ACK response
during reception. The ACK response and the logical “0” output show the same
waveform.
CEC