TMPM330 - Keil

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Type Function # of Pins Pin Name 91 PC0 AN0 92 PC1 AN1 93 PC2 AN2 94 PC3 AN3 95 PD0 AN4 96 PD1 AN5 97 PD2 AN6 98 PD3 AN7 99 PD4 AN8 100 PD5 AN9 Input/ Output I I I I I I I I I I I I I I I I I I I I Under development Table 2.2 Pin Names and Functions (5/5) Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Function TMPM330 (rev0.4) 2-8 Programma ble Pull-up/ Pull down Schmitt trigger TMPM330 Programma ble Open Drain Output Pull up - - Pull up - - Pull up - - Pull up - - Pull up - - Pull up - - Pull up - - Pull up - - Pull up - - Pull up - - (Note 1) Be sure to set TEST1 through 4 to OPEN. (Note 2) Be sure to set MODE pin to DVSS. (Note 3) VREFH and AVSS pins must be connected to GND pin even if the A/D converter is not used. (Note 4) Nch open drain port. Pin Layout and Pin Functions
2.3 Pin Names and Power Supply Pins Under development Table 2.3 Pin Names and Power Supplies Pin name Power supply PA DVCC3 PB DVCC3 PC DVCC3 PD DVCC3 PE DVCC3 PF AVCC3 PG DVCC3 PH DVCC3 PI DVCC3 PJ DVCC3 PK DVCC3 X1, X2 CVCC XT1, XT2 DVCC3 RESE DVCC3 NMI DVCC3 MODE DVCC3 2.4 Pin Numbers and Power Supply Pins Table2.4 Pin Numbers and Power Supplies Power supply Pin number Voltage range DVCC 14, 62 AVCC REGVCC 5 76 2.7V~3.6V CVCC 71 TMPM330 (rev0.4) 2-9 TMPM330 Pin Layout and Pin Functions
Page 1 and 2: 1. Overview and Features Under deve
Page 3 and 4: Under development (13) Standby mode
Page 5 and 6: 2. Pin Layout and Pin Functions Und
Page 7 and 8: Pin No. Under development Table 2.1
Page 9 and 10: Type Function Function/ BOOT Functi
Page 11: Type Function/ Debug Function # of
Page 15 and 16: 4. Memory map 4.1 Memory map 0x4008
Page 17 and 18: 0x4008 FFFF 0x4000 0000 0x2000 1FFF
Page 19 and 20: X1 X2 XT1 XT2 5.2.2 Clock System Bl
Page 21 and 22: SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
Page 23 and 24: STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
Page 25 and 26: CKSEL 5.3.2.5 System Clock Selectio
Page 27 and 28: 5.4.2 Main System Clock External os
Page 29 and 30: 5.4.4 System Clock Pin Output Funct
Page 31 and 32: 5.8.1 IDLE Mode Under development T
Page 33 and 34: Under development 5.8.4 Low power C
Page 35 and 36: 5.8.7 Warm-up Under development TMP
Page 37 and 38: Under development 5.8.8.3 Transitio
Page 39 and 40: 6.2.2 Generation Under development
Page 41 and 42: Under development Table 6-1 List of
Page 43 and 44: Under development TMPM330 (rev0.4)
Page 47 and 48: 6.3.6 Interrupt Service Routine Und
Page 49 and 50: 6.4.2 CG Interrupt Mode Control Reg
Page 51 and 52: 6.4.4 CG Interrupt Mode Control Reg
Page 55 and 56: 6.4.7 NMI Flag Register Under devel
Page 57 and 58: 7 Input/Output Ports 7.1 Port regis
Page 59 and 60: Under development Port A input enab
Page 61 and 62: 7.1.3 Port C (PC0~PC3) Under develo
Page 63 and 64:
7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Page 123 and 124:
Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
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9.3.12 Parity Control Circuit 9.3.1
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Under development 9.3.17 Configurat
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Under development 9.4 Register Desc
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9.4.4 Mode control register 0 SC0MO
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Under development : This is a statu
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Page 141 and 142:
9.4.10 TX FIFO configuration regist
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9.5 Operation in Each Mode 9.5.1 Mo
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SCLK input mode Under development T
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Receiving data SCLK output mode Rec
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Transmit and receive (full-duplex)
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SCLK input mode Under development T
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9.5.2 Mode 1 (7-bit UART Mode) Unde
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9.5.4 Mode 3 (9-bit UART) Under dev
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10. Serial Bus Interface (SBI) Chan
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10.2 Control Under development TMPM
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SBIxCR0 10.4 Control Registers in t
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Page 165 and 166:
Under development Table 10-1 Base C
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SBIxBR0 bit Symbol I2SBI0 Under dev
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10.5 Control in the I 2 C Bus Mode
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Under development 10.5.6 Configurin
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Master A Master B Under development
Page 175 and 176:
Under development 10.6 Data Transfe
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SCL pin Write to SBIxDBR SDA pin I
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Slave mode ( = “0”) Under devel
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10.6.4 Generating the Stop Conditio
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Under development 10.7 Control in t
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SBIxDBR SBIxCR2 Under development S
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10.7.1 Serial Clock SCK pin output
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10.7.2 Transfer Modes Under develop
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SCK pin SIOF SO pin bit 6 Under dev
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SCK pin (output) SO pin SI pin IN
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11.2 Registers 11.2.1 Control Regis
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Under development 11.2.5 Software R
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Under development 11.2.7 Receive Bu
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Under development TMPM330 (rev0.4)1
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Under development 11.2.10 Receive C
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Under development 11.2.11 Transmit
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Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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Page 235 and 236:
(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
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ADMOD1 Under development A/D Mode C
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Page 259 and 260:
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ADREG2AL ADREG2AH ADREG3BL ADREG3BH
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ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
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13.4 Description of Operations 13.4
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Page 271 and 272:
Under development 3. Fixed channel
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13.4.5 High-priority Conversion Mod
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Under development 14. Watchdog Time
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14.3 Control Registers Under develo
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14.4 Control Register Under develop
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15.3 Control Register Under develop
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MINR Under development (2) Minute c
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DAYR DATER Under development (4) Da
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YEARR YEARR Under development (8) Y
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15.5 Operational description (1) Re
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3. Disabling the clock Under develo
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(2) 1Hz clock Under development TMP
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16.1 Addresses [1] Port [1/4] ADR
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[1] Port 3/4] ADR Register name AD
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[2] 16-bit timer [1/4] ADR Registe
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[2] 16-bit timer [3/4] ADR Registe
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Under development [3] Serial bus in
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[5] 10-bit A/D converter (A/DC) ADR
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[10] Remote control signal preproce
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Under development JEDEC compliant f
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Page 313 and 314:
User Boot Mode Under development (1
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(Step-5) Under development TMPM330
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17.2.3 Single Boot Mode Under devel
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Page 323 and 324:
(1) Configuration for Single Boot M
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(5) Restrictions on internal memori
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Under development Table 17-7 Transf
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Under development Table 17-9 Transf
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(6) Operation of Boot Program Under
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Page 335 and 336:
Under development returns to the st
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Under development 3) Show Product I
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Under development 4) Chip Erase com
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5) Acknowledge Responses Under deve
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Point A Point B Point C Point D Und
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Start Are all bytes the same? YES A
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(7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Page 353 and 354:
Page 355 and 356:
Page 357 and 358:
Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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