TMPM330 - Keil

6.4.2 CG Interrupt Mode Control Register A
Under development
TMPM330 (rev0.4) 6-12
TMPM330
7 6 5 4 3 2 1 0
IMCGA bit Symbol EMCG02 EMCG01 EMCG00 EMST01 EMST00 INT0EN
Read/Write R R/W R R R/W
After reset 0 0 1 0 0 0 0 0
Function
“0” is read. Active state setting of INT0 standby
clear request. (101~111: setting
prohibited)
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
Active state of INT0
standby clear request
00: -
01: Rising edge
10: Falling edge
11: Both edges
“0” is read. INT0 clear
input
0: Disable
1: Enable
15 14 13 12 11 10 9 8
bit Symbol EMCG12 EMCG11 EMCG10 EMST11 EMST10 INT1EN
Read/Write R R/W R R R/W
After reset 0 0 1 0 0 0 0 0
Function “0” is read. Active state setting of INT1 standby
clear request. (101~111: setting
prohibited)
Active state of INT1
standby clear request
“0” is read. INT1 clear
input
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
00: -
01: Rising edge
10: Falling edge
11: Both edges
0: Disable
1: Enable
23 22 21 20 19 18 17 16
bit Symbol EMCG22 EMCG21 EMCG20 EMST21 EMST20 INT2EN
Read/Write R R/W R R R/W
After reset 0 0 1 0 0 0 0 0
Function “0” is read. Active state setting of INT2 standby
clear request. (101~111: setting
prohibited)
Active state of INT2
standby clear request
“0” is read. INT2 clear
input
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
00: -
01: Rising edge
10: Falling edge
11: Both edges
0: Disable
1: Enable
31 30 29 28 27 26 25 24
bit Symbol EMCG32 EMCG31 EMCG30 EMST31 EMST30 INT3EN
Read/Write R R/W R R R/W
After reset 0 0 1 0 0 0 0 0
Function “0” is read. Active state setting of INT3 standby
clear request. (101~111: setting
prohibited)
Active state of INT3
standby clear request
“0” is read. INT3 clear
input
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
00: -
01: Rising edge
10: Falling edge
11: Both edges
0: Disable
1: Enable
(Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
(Note 2) Please specify the bit for the edge first and then specify the bit for the
. Setting them simultaneously is prohibited.
Interrupts