TMPM330 - Keil

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10.1 Configuration The configuration is shown in Fig. 10-1. fsys/2 SIO clock control Frequency Divider SBICR2 SBISR SBI control register 2/ SBI status register I 2 C bus address register Under development INTSBI0 interrupt request I 2 C bus Transfer control Noise clock synchronization + circuit canceller control Shift register I2CAR SBIDBR SBI data buffer register Fig. 10-1 SBI Block Diagram TMPM330 (rev 0.4) 10-2 SIO data control I 2 C bus data control SBI control registers 0,1 Noise canceller SBICR0,1 SBIBR0 SBI baud rate register 0 SCL SCK Input/ output control SO SI SDA TMPM330 SCK SDA SO SCLO SIO Serial Bus Interface (SBI)
10.2 Control Under development TMPM330 (rev 0.4) 10-3 TMPM330 The following registers control the serial bus interface and provide its status information for monitoring. • Serial bus interface control registers 0 (SBIxCR0) • Serial bus interface control registers 1 (SBIxCR1) • Serial bus interface control registers 2 (SBIxCR2) • Serial bus interface buffer registers (SBIxDBR) • I 2 C bus address register (SBIxI2CAR) • Serial bus interface status registers (SBIxSR) • Serial bus interface baud rate registers 0 (SBIxBR0) Register name (address) The functions of these registers vary, depending on the mode in which the SBI is operating. For a detailed description of the registers, refer to “10.5 Control in the I2C Bus Mode” and “10.7 Control in the Clock-synchronous 8-bit SIO Mode”. The addresses of each register are shown below. Channel 0 Channel 1 Channel 2 Serial bus interface control register 0 SBI0CR0 0x4002_0000 SBI1CR0 0x4002_0020 SBI2CR0 0x4002_0040 Serial bus interface control register 1 SBI0CR1 0x4002_0004 SBI1CR1 0x4002_0024 SBI2CR1 0x4002_0044 Serial bus interface SBI0CR2 SBI1CR2 SBI2CR2 control register 2 Serial bus interface (reading) SBI0SR 0x4002_0010 (reading) SBI1SR 0x4002_0030 (reading) SBI2SR 0x4002_0050 status register (writing) (writing) (writing) Serial bus interface baud rate register 0 SBI0BR0 0x4002_0014 SBI1BR0 0x4002_0034 SBI2BR0 0x4002_0054 Serial bus interface data buffer register SBI0DBR 0x4002_0008 SBI1DBR 0x4002_0028 SBI2DBR 0x4002_0048 I 2 C bus address register SBI0I2CAR 0x4002_000C SBI1I2CAR 0x4002_002C SBI2I2CAR 0x4002_004C Serial Bus Interface (SBI)
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1. Overview and Features Under deve
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Under development (13) Standby mode
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2. Pin Layout and Pin Functions Und
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Pin No. Under development Table 2.1
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Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
Page 107 and 108: 9 Serial Channel (SIO) 9.1 Features
Page 109 and 110: • Mode 0 (I/O Interface mode) /LS
Page 111 and 112: Under development 9.3 Operation of
Page 113 and 114: Under development (Note 1) The pres
Page 115 and 116: Under development (Note 1) The pres
Page 117 and 118: • Example baud rate setting: Unde
Page 119 and 120: fc [MHz] Under development Table 9-
Page 121 and 122: Under development TMPM330 (rev 0.4)
Page 123 and 124: Under development I/O interface mo
Page 125 and 126: • Handshake function Data write t
Page 127 and 128: 9.3.10 Transmit FIFO Buffer Under d
Page 129 and 130: 9.3.12 Parity Control Circuit 9.3.1
Page 131 and 132: Under development 9.3.17 Configurat
Page 133 and 134: Under development 9.4 Register Desc
Page 135 and 136: 9.4.4 Mode control register 0 SC0MO
Page 137 and 138: Under development : This is a statu
Page 141 and 142: 9.4.10 TX FIFO configuration regist
Page 143 and 144: 9.5 Operation in Each Mode 9.5.1 Mo
Page 145 and 146: SCLK input mode Under development T
Page 147 and 148: Receiving data SCLK output mode Rec
Page 149 and 150: Transmit and receive (full-duplex)
Page 151 and 152: SCLK input mode Under development T
Page 153 and 154: 9.5.2 Mode 1 (7-bit UART Mode) Unde
Page 155 and 156: 9.5.4 Mode 3 (9-bit UART) Under dev
Page 157: 10. Serial Bus Interface (SBI) Chan
Page 161 and 162: SBIxCR0 10.4 Control Registers in t
Page 165 and 166: Under development Table 10-1 Base C
Page 167 and 168: SBIxBR0 bit Symbol I2SBI0 Under dev
Page 169 and 170: 10.5 Control in the I 2 C Bus Mode
Page 171 and 172: Under development 10.5.6 Configurin
Page 173 and 174: Master A Master B Under development
Page 175 and 176: Under development 10.6 Data Transfe
Page 177 and 178: SCL pin Write to SBIxDBR SDA pin I
Page 179 and 180: Slave mode ( = “0”) Under devel
Page 181 and 182: 10.6.4 Generating the Stop Conditio
Page 183 and 184: Under development 10.7 Control in t
Page 185 and 186: SBIxDBR SBIxCR2 Under development S
Page 187 and 188: 10.7.1 Serial Clock SCK pin output
Page 189 and 190: 10.7.2 Transfer Modes Under develop
Page 191 and 192: SCK pin SIOF SO pin bit 6 Under dev
Page 193 and 194: SCK pin (output) SO pin SI pin IN
Page 195 and 196: 11.2 Registers 11.2.1 Control Regis
Page 197 and 198: Under development 11.2.5 Software R
Page 199 and 200: Under development 11.2.7 Receive Bu
Page 201 and 202: Under development TMPM330 (rev0.4)1
Page 203 and 204: Under development 11.2.10 Receive C
Page 205 and 206: Under development 11.2.11 Transmit
Page 207 and 208: Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
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ADMOD1 Under development A/D Mode C
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ADREG2AL ADREG2AH ADREG3BL ADREG3BH
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ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
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13.4 Description of Operations 13.4
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Under development 3. Fixed channel
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13.4.5 High-priority Conversion Mod
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Under development 14. Watchdog Time
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14.3 Control Registers Under develo
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14.4 Control Register Under develop
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15.3 Control Register Under develop
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MINR Under development (2) Minute c
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DAYR DATER Under development (4) Da
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YEARR YEARR Under development (8) Y
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15.5 Operational description (1) Re
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3. Disabling the clock Under develo
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(2) 1Hz clock Under development TMP
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16.1 Addresses [1] Port [1/4] ADR
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[1] Port 3/4] ADR Register name AD
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[2] 16-bit timer [1/4] ADR Registe
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[2] 16-bit timer [3/4] ADR Registe
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Under development [3] Serial bus in
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[5] 10-bit A/D converter (A/DC) ADR
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[10] Remote control signal preproce
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Under development JEDEC compliant f
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User Boot Mode Under development (1
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(Step-5) Under development TMPM330
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17.2.3 Single Boot Mode Under devel
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(1) Configuration for Single Boot M
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(5) Restrictions on internal memori
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Under development Table 17-7 Transf
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Under development Table 17-9 Transf
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(6) Operation of Boot Program Under
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Under development returns to the st
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Under development 3) Show Product I
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Under development 4) Chip Erase com
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5) Acknowledge Responses Under deve
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Point A Point B Point C Point D Und
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Start Are all bytes the same? YES A
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(7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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