PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 44:LCD Interface Signal List (Continued)Signal Name Type DescriptionL_FCLK_RD Output Frame clock used by the LCD display module to signal the start of a new frame ofpixels that resets the line pointers to the top of the screen. Also, it is used by active(TFT) display module as the vertical synchronization signal. For active displays,this is also referred to as the “vertical sync signal” or “VSYNC”.Read signal during reads from an LCD panel with internal frame buffers.L_BIAS Output AC bias used to signal the LCD display module to switch the polarity of the powersupplies to the row and column axis of the screen to counteract DC offset. In active(TFT) mode, it is used as the output-enable to signal when data should be latchedfrom the data pins using the pixel clock.L_CS Output No connect for active (TFT) and passive (STN) panels.For smart panels, L_CS is used as chip-select signal.L_VSYNC Input Refresh sync signal from smart panels. No connect for active (TFT) and passive(STN) panels.Not all signals are required for all modes of operation. Refer to the LCD panel referencedocumentation specific to the manufacturer for information on:Note• Specific signals required for correct LCD operation• Correct names of the signals used by the LCD panel manufacturer13.2 Modes of Operation Overview13.2.1 Passive Color Mode13.2.1.1 SignalsPassive color displays send dithered data to the panel. Each bit of color data requires three pins.For passive color displays, see Table 45 for description of the pins required for connections betweenthe PXA3xx processor family and the LCD panel.Table 45:Passive Display Pins RequiredPXA30x,PXA31x,PXA32xProcessorPinLCD Panel Pin Pin Type 1 DefinitionLDD D Output Data lines used to transmit 2 2/3 data values at a time to theLCD display. Groupings of three pin values represent onepixel (red, green, and blue data values).L_PCLK_WR Pixel_Clock Output Pixel Clock – used by the LCD display to clock the pixel datainto the line shift register.L_LCLK_A0 Line_Clock Output Line Clock – used by the LCD display to signal the end of aline of pixels. Line clock transfers a line of pixels from the shiftregister to the screen and increment the line pointer.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 108April 6, 2009, Released
Table 45:Passive Display Pins Required (Continued)PXA30x,PXA31x,PXA32xProcessorPinLCD Panel Pin Pin Type 1 DefinitionL_FCLK_RD Frame_Clock Output Frame Clock – used by the LCD displays to signal the start ofa new frame of pixels. Frame clock resets the line pointer tothe top of the screen.L_BIAS Bias Output Bias – used to signal the LCD display that it should switch thepolarity of the power supplies to the row and column axis ofthe screen to counteract DC offset.N/A Vcon 2 N/A Contrast voltage – adjustable voltage input to LCD panel.External voltage circuitry is required (no pin is provided onthe PXA3xx processor family).NOTE:1. “Pin Type” is in reference to the PXA3xx processor family. Therefore, outputs are pins that drive a signal from theprocessor to another device.2. Vcon is a signal external to the PXA3xx processor family.3. Names used for “LCD Panel Pin” are representative names and do not match those on all LCD panels. Similarly, notall signals are required for all modes of operation. Refer to the LCD panel reference documentation for information onspecific signals required for correct LCD operation and correct names of the signals used by the LCD panelmanufacturer.13.2.1.2 Schematics / Block DiagramSee Figure 43 for an illustration of typical connections for a single-scan color passive panel. Thefigure indicates the top, left pixel color bits.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 109
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TablesTable 1: How Design Guide Cha
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PXA3xx Design Guide - Marvell

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