PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideAnother factor that impacts the PCB keep-out area requirements is the use of a socket. Whilesockets are only used during product development, the sockets require larger keep-out areas toaccommodate mechanical mounting holes. The sockets often require backing plates that prevent theuse of decoupling components under the IC package where the components are most effective.2.2 Power Supply Decoupling RequirementsEach major power plane section or feeder trace requires a 4.7 µF or larger bulk decoupling capacitornear the processor in addition to the recommended high-speed decoupling capacitors shown inTable 5. If the voltage regulator for a given voltage domain is within 0.5” of the PXA3xx processorfamily, designers can use the bulk decoupling at the voltage regulator output as the bulk decouplingat the processor.See Table 5 for decoupling capacitor recommendations for each voltage domain.Note• These interface guidelines are based on basic understandings, educatedestimations, and simulation data.• All decoupling capacitors should be placed within 0.5” inch of the PXA300,PXA310, and PXA320 processor. The decoupling capacitors can be placed on theboard’s bottom side as long as the length restrictions are met. Each decouplingcapacitor must be connected to the VCC and VSS planes by private vias – noshared vias.• All VCC planes should be routed as planes. A thick trace (> 250 mils) is onlyallowed for very low frequency interfaces. The VSS plane can be a common plane.• In actual cell phone or PDA designs, the length of VCC planes from the voltageregulator to the PXA3xx processor family should not exceed 3 inches in general.For very slow interfaces, this length can be extended up to 4 inches. DDR, USBand DFI have dedicated guidelines.• If a signal jumps from power plane reference to ground plane reference, a stitchdecap between that power and ground is recommended. If a signal jumps from onepower plane reference to another power plan reference, stitch both power planesto ground. Stitching decaps should be close to where the signal changesreference. Stitching between power planes could cause noise coupling.• Marvell recommends using 1.0 µF, 0402 size, X6S dielectric; ESL 500pH, ESR11.2 MΩ high-frequency decoupling capacitors for the PXA3xx processor familypower domains. One part that meets these specs is the TDK P/NC1005X5ROJ105. This part number is provided as a reference only. There aremany other manufacturers who sell parts that meet these specifications (ESR andESL targets).Table 5:Decoupling Capacitors Per Voltage Domain RecommendationsDomain PCB Decoupling Voltage Level (TYP) GroupVCC_BBATT 2 x 1.0 µF x 0402 3.0 V BATTVCC_APPS 5 x 1.0 µF x 0402 1.15 V LVTVCC_SRAM 2 x 1.0 µF x 0402 1.15 V LVTVCC_MVT 4 x 1.0 µF x 0402 1.8 V MVTVCC_BG 1 x 1.0 µF x 0402 1.8 V MVTVCC_PLL 2 x 4.7 µF x 0402 1.8 V MVTDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 26April 6, 2009, Released
Table 5:Decoupling Capacitors Per Voltage Domain Recommendations (Continued)Domain PCB Decoupling Voltage Level (TYP) GroupVCC_OSC13M — 1.8 V MVTVCC_IO1 1 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 V HVTVCC_IO3 1 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 V HVTVCC_IO4 2 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 VNOTE: PXA32x processor onlyVCC_IO6 2 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 VNOTE: PXA32x processor onlyHVTHVTVCC_USB 3 x 1.0 µF x 0402 3.3 V HVTVCC_DF See Table 7 1.8 V, 3.0 V, 3.3V HVTVCC_CI 2 x 1.0 μF x 0402 1.8 V, 3.0 V, 3.3V HVTVCC_MEM See Table 6 1.8 V HVTVCC_CARD1 2 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 V HVTVCC_CARD2 2 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 V HVTVCC_LCD 2 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 V HVTVCC_MSL 2 x 1.0 µF x 0402 1.8 V, 3.0 V, 3.3 V HVTVCC_BIASVCC_ULPI3.3 VNOTE: PXA30x and PXA31x processor only1.8 VNOTE: PXA31x processor onlyHVTHVTVCC_TSI 1 x 1.0 µF x 0402 3.3 VNOTE: PXA32x processor onlyHVTTable 6:VCC_MEM (DDR DRAM) Decoupling RecommendationsDevice Recommendation NotesPMIC Series Resistanceand InductancePMIC DC Set Point ErrorToleranceR = 20 µF; ESL ~ 1 nHESR
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Page 11 and 12: Copyright © 2009 MarvellDoc. No. M
Page 13 and 14: Figure 42: SPI Protocol Interface B
Page 15: TablesTable 1: How Design Guide Cha
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PXA3xx Design Guide - Marvell

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