PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign Guidethe USB. The port 2 multiplexor also provides an interface that allows the UDC port, UHC port 2, andthe UHC port 3 to connect to single-ended I/O through the GPIOs.The PXA30x processor or PXA32x processor OTG transceiver consists of one pullup resistor andtwo pull-down resistors on each D+ and D-.• The resistors are enabled using the “USB Port 2 Output Control Register (UP2OCR)”pull-up/pull-down enable bits (DPPUBE, DMPUBE, DPPUE, DMPUE, DPPDE, DMPDE). SeeFigure 61 for illustration of the on-chip host port 2 transceiver pad with the pull-up and pull-downresistors.• As shown in Figure 61, SW3 is enabled for both D+ and D- when host port 2 is being used forUSB host-controller data.• As shown in Figure 61, SW1 on the D+ pad is enabled and SW1 on the D- pad is disabled whenhost port 2 is being used for USB device-controller data.• As shown in Figure 61, SW2 on the D+ and D- pads is disabled when host port 2 is being usedfor USB device-controller data, but SW2 is enabled and disabled by hardware when the UDC isidle and receiving data from an upstream device as specified in the Pullup/Pulldown ResistorsEngineering Change Notice to the USB 2.0 Specification.See Table 56 for the list of switch settings used for the USB host and USB device controller I/O.Figure 61: Host Port 2 OTG TransceiverUSB Host Port 2 Transceiver PadUP2OCR[DPPUBE/DMPUBE]UP2OCR[DPPUE/DMPUE]UDC txenUHC port 2 txenSW2R PU2900 - 1.575 K OhmsSW1UP2OCR[HXOE]R PU1UDC TxD+/TxD-UP2OCR[HXS]ENB525 - 1.515 K OhmsUHC Port 2 TxD+/TxD-D+/D-SW3RxD+/RxD-UP2OCR[DPPDE/DMPDE]R PD14.25 - 24.8 K OhmsDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 144April 6, 2009, Released
Table 56:Host Port 2 OTG Transceiver Switch Control SettingsControllerSelectedD+ Transceiver D- TransceiverSW1† SW2† SW3† SW1† SW2† SW3†USB Host Disabled Disabled Enabled Disabled Disabled EnabledUSB Device Enabled HardwarecontrolledDisabled Disabled Disabled Disabled† SW1, SW2 and SW3 refer to the switches shown in Figure 61.NoteSee the Marvell ® PXA30x Processor and PXA31x Processor Vol. IV: Serial ControllerConfiguration Developers Manual for programming requirements for disabling andenabling the transceiver and pullup/pulldown resistors for USB Host Port 2 and forS2/D3/C4 and S0/D2/C2 mode operation.17.4.4 Interface to External Transceiver (OTG)If the internal OTG transceiver is not used, the USB device controller (UDC) contains control, status,and interrupt registers to provide seamless interface to external transceivers.External transceivers provide D+, D- and Vbus driver to the USB cable. In this mode, the D+ and D-signals of the USB are output through GPIO pads with the “USB Port 2 Output Control Register(UP2OCR)” [SE0S] using the control multiplexors to select between UDC and D+, D-, andtransmit-enable signals of USB host controller.In addition, “USB Port 2 Output Control Register (UP2OCR)” provides the following:• External transceiver suspend (EXSUS) control output bit• External transceiver speed (EXSP) control output bit• External transceiver interrupt input to interface to the external transceiver.See Figure 62 for an illustration of the PXA30x processor or PXA32x processor OTG connections toan external transceiver.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 145
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