PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 85:PXA3xx Processor Family Schematic Checklist (Continued) Signal Name Category DetailsKeypad InterfaceKP_MKINx andKP_DKINxNo connectionNo external pull-down resistor is required. The PXA3xxprocessor family includes the required internal pull-down resistorto ground.Universal Subscriber ID (USIM) InterfaceSC_IO20 KΩ pull-up resistorto VCC_CARD1.Required only if using the USIM controller. See Section 26,USIM Controller Interface for additional information.Leave the SC_IO signal disconnected if the USIM controller isnever used.Universal Serial Bus Device Controller (UDC)USBOTG_P1.5 KΩ pull-up resistorusing GPIO signal.Some designs may be able to use the internal pull-up resistor.See Section 17, USB 1.1 Full Speed OTG and Device Controller(PXA30x processor or PXA32x processor only) for additionalinformation.Signal must remain floating or pull-up (1.5 KΩ) to minimizepower use during standby, sleep, and deep sleep modes.USBOTG_N Floating or pull-up Signal must remain floating or pull-up (10 K - 100 KΩ) tominimize power use during standby, sleep, and deep sleepmodes.All Signals — See Section 17, USB 1.1 Full Speed OTG and Device Controller(PXA30x processor or PXA32x processor only) for differentpossible configurations.Universal Serial Bus Host Controller (UHC)All Signals — See Section 20, USB 1.1 Host Interface for different possibleconfigurations.Host Ports 1 and 2 Termination See Section 20.3.1, USB Host Differential Connection (Port 1) ,and Section 20.3.2, USB Host Connections (Port 2) whichshows a block diagrams detailing host port termination andconnection requirements.General Purpose IO (GPIO) ControllerGPIOxPull-down unusedGPIOx signals.Unused GPIO signals can be either pull-down or driven asoutputs to minimize power use. These states are softwareconfigurable.nGPIO_RESET Weak pull-up nGPIO_RESET should have a weak pull-up (50 KΩ). Theinternal pull-up can be disabled via software.JTAG DebugDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 206April 6, 2009, Released
Table 85:PXA3xx Processor Family Schematic Checklist (Continued) Signal Name Category DetailsnTRSTTCKFor JTAG operation,must be driven fromboth the system resetand the JTAG toolsindependently withoutcontention.For JTAG operation,use 10K ohm pulldownresistor.During power-up, nTRST must be driven from low to high eitherbefore or at the same time as nRESET.During power-up, 10 µs must elapse after nTRST is de-assertedbefore proceeding with any JTAG operation.See Section 9, JTAG Debug for additional information.Pullup to VCC_BBATT using a 10K resistor.See Section 9, JTAG Debug for additional information.TMS Floating or pullup. Signal must remain floating or pullup (10-100 KΩ) to minimizepower use during standby, sleep, and deep sleep modes.TDI Floating or pullup Signal must remain floating or pull-up (10-100 KΩ) to minimizepower use during standby, sleep, and deep sleep modes.TDONo pullups orpulldowns requiredConnect from JTAG connector. No pull-ups or pull-downsrequired.nSRST Bidirectional nSRST is not a signal on the PXA3xx processor family. TheARM standard JTAG connector specifies the nSRST should bebidirectional and allow JTAG to both sense and drive the CPUreset (nRESET). A JTAG module connected to an XScale ®processor must be able to control the nRESET signal in order toenable proper JTAG debugger communication.See Section 9, JTAG Debug for additional information.Typical Voltage Rail ConnectionsPMIC OUTPUT 1 Voltage Supply Regulated Main battery voltage, nominally 3.0V (not to exceedmax 4.0V) to power VCC_BBATTPMIC OUTPUT 2 Voltage Supply VCC_MEM @ 1.8VPMIC OUTPUT 3 Voltage Supply VCC_BG, VCC_MVT, VCC_PLL, VCC_OSC13M connectedtogether @ 1.8VPMIC OUTPUT 4 Voltage Supply VCC_LCD, VCC_MSL, VCC_CI, VCC_DF connected togetherat 1.8VPMIC OUTPUT 5 Voltage Supply VCC_APPS dynamically adjustablePMIC OUTPUT 6 Voltage Supply VCC_SRAM dynamically adjustablePMIC OUTPUT 7 Voltage Supply VCC_IO1, VCC_IO3, VCC_IO4 and VCC_IO6 connectectedtogether at 1.8V, 3.0V or 3.3V (depends on voltage required forexternal components)NOTE: VCC_IO4 and VCCIO6 only apply to the PXA32xProcessorPMIC OUTPUT 8 Voltage Supply VCC_CARD1 and VCC_CARD2 connected together at 1.8V or3.0V (+/- 10%) to USIM or Removable storage card. This can besupplied by another regulator passing through an analog powerswitch. This supply can be connected to another supply of theappropriate voltage is USIM functions are not used.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 207
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Figure 42: SPI Protocol Interface B
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PXA3xx Design Guide - Marvell

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