PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 36: VLIO Interface Block Diagram - Operation on DFI with AA/D Compatible VLIO DeviceDF_IOA/DData Flash Interface (DFI)nBEnLLAnLUAnCS2 or nCS3DF_CLE_nOEDF_ALE_WExMASKnADVnADV2CSOEWEx16 VLIO DeviceAA/D OperationREADYRDY11.5.4 PC Card (PCMCIA) Operation (PXA32x only)The PXA32x process requires external glue logic to complete the 16-bit PC card socket interface.Only 1-socket solutions are possible.Figure 37 shows a general solution for a PC-card configuration:The pull-ups shown are included as specified in the PC Card Standard, Volume 2, ElectricalSpecification, PCMCIA/JEITA. Low-power systems must remove power from the pull-ups duringsleep to avoid unnecessary power consumption.GPIO or memory-mapped external registers control the reset of the 16-bit PC card interface, powerselection (VCC and VPP), and drive enables. The INPACK# signal is not used.Figure 37 shows the logical connections necessary to support hot-insertion capability:For dual-voltage support, level-shifting buffers are required for all PXA32x input signals.Hot-insertion capability requires that each socket be electrically isolated from the remainder of thememory system. If hot-insertion capability is not required, then some of the logic shown in thefollowing diagrams is eliminated.Use software to set the MECR[NOS] and MECR[CIT] bits. MECR[NOS] indicates the number ofsockets that the system supports, while MECR[CIT] is written when the card is in place. Input pinsnPWAIT and nIOIS16 are three-stated until the card detect (CD) signal is asserted. To achieve thisstate, software programs the MECR[CIT] bit when a card is detected. If the MECR[CIT] is 0, thenPWAIT and nIOIS16 inputs are ignored.11.5.4.1 PC Card Block DiagramsThis section describes how to interface a one-socket PC card adapter to the PXA32x memorycontroller.Unknown behavior may result if connected to a PC card or CF card that is powered and directlyattached to the memory bus at reset, depending on the states of the remaining card interfacesignals.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 90April 6, 2009, Released
To prevent erroneous nPCE assertions during reset, the board must have board-level 4.7 KΩpull-ups.Refer to the Marvell ® PXA32x Processor Electrical, Mechanical, and Thermal Specification foradditional information. The weak (50 KΩ nominal) on-chip pull-downs are released when the RDHbit is cleared. Subsequently, contentions through the two board-level pull-ups occur only duringPC-card accesses.External Logic for PC-Card Implementation Block DiagramSee Figure 37 for illustration of the minimal glue logic needed for a PC-card system. The illustrationshows:• Data transceivers• Address buffersFigure 37 does not show all level-shifting buffers that may be required to interface between thePC-Card and the DFI interface.The transceivers are enabled by the PSKTSEL signal. The DIR pin of the transceiver is driven by theRDnWR pin. A GPIO is used for the three-state signal of the address and nPWE lines. These signalsmust be three-stated because they are used for memories other than the card interface. The CardDetect signals are driven by the single device.Figure 37: PC-Card Block Diagram - Operation in AA/D Muxed ModenXCVRENData Flash Interface (DFI)DF_IOnLUAnLLAnIOIS16, nPWAITLatchLatchDF_CLE_nOE, DF_ALE_WExnPIOR, nPIOWGPIOz 4 , GPIOa 4GPIOb 4GPIOc 4XCVRDRDnWR 7nPCE1 5 , nPCE2 5 , nPREG 5A 6AnIOIS16, WAIT#OE#, WE#nIOR, nIOWCD1#, CD2#ReadyWPPC-CardRequired >=10 KΩ 10KΗpullup notshown forWAIT#, CD1#,CD2#,READY,11.5.4.2 PC Card Layout NotesPull-up resisters shown in Figure 37 must be 10 KΩ or greater in value. Refer to Marvell ® PXA30x,PXA31x, and PXA32x Processor Electrical, Mechanical, and Thermal Specification timinginformation.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 91
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PXA3xx Design Guide - Marvell

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