PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 62April 6, 2009, Released
DDR Memory Interface (EMPI Bus)Overview10 DDR Memory Interface (EMPI Bus)This section describes guidelines for connecting the PXA3xx processor family External Memory PinInterface (EMPI) to external DDR memory. Be sure to reference vendor-specific examples ofschematics and timing diagrams for SDRAM devices.All EMPI memory device types are discussed in this section, which includes design considerationsfor DDR devices as discussed in Marvell ® PXA30x, PXA31x, and PXA32x Processors Vol. II:Memory Controller Configuration Developers Manual, “Section 1: Dynamic Memory Controller”.10.1 OverviewThe EMPI for the PXA3xx processor family supports the following:• DDR SDRAM Clock• Up to 30 MTps during ring oscillator (S0/D0CS/C0) mode• 130 MTps during run/turbo (S0/D0/C0) modeRefer to Marvell ® PXA30x, PXA31x, and PXA32x Processors Vol. II: Memory ControllerConfiguration Developers Manual, “Section 1: Dynamic Memory Controller” for the physicaladdresses used to configure and map the external memory.The SDRAM must always reside on the EMPI bus and must always be controlled by the DynamicMemory Controller (DMC). The maximum supported configurations on the EMPI bus is as follows:• PXA30x Processor and PXA31x Processor DDR SDRAM maximum bus width is 16-bits (x16)• PXA32x DDR SDRAM maximum bus width is 32-bits (x32)NoteThe above configurations describe only the memory devices on the EMPI bus. Anyallowable memory devices may be placed on the data-flash interface (DFI) withoutregard to the memory devices on the EMPI bus.10.2 SignalsSee Table 17 for the list of EMPI signals.Table 17:SignalNamePXA30x DDR SDRAM I/O SignalsDirection Polarity DescriptionMD Bidirectional N/A Bidirectional data for external static and dynamic memory.NOTE: PXA30x Processor and PXA31x Processor only use MDMAMASDMA10Output N/A Output address to all memory typesNOTE: MA are always connected to DDR BA signalsregardless of how many row/col addresses used.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 63
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PXA3xx Design Guide - Marvell

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