PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign GuideLength of (TL2A+TL3A) = Length of (TL2B+TL3B) +/- 0.1"• Refer to matching rules for length matching requirement between MD and DQS.Figure 21: Signal: DQSTable 23:DQS Signals Routing Recommendations for x32 - 2 (x16) devicesTraceMaxLengthTrace WidthSpacing between this Signal traceand any other Signal traceLayerTL1 (Breakout) 0.3” 3 mils 4 mils HDITL2A and TL2B 0.7” 4 mils 5 mils Buried Micro StripTL3A and TL3B 0.2” 3 mils 4 mils HDI• Recommended maximum via count, including breakout via = 8• Total length of (TL1+TL2A+TL3A) Max = 1.1" and• Total length of (TL1+TL2B+TL3B) Max = 1.1"• Length Matching within DQS (applies to all 4 DQS Signals):Length of (TL2A+TL3A) = Length of (TL2B+TL3B) +/- 0.1"• Refer to matching rules for length matching requirement between DQS and SDCLK.• Refer to matching rules for length matching requirement between DQS and MD/DQM.10.4.3.1 Length Matching between DQS and MD/DQM for x32 - 2 (x16) DevicesThere are four DQS byte lanes: DQS, DQS, DQS and DQS.• Every data signal between MD and DQM should be length matched to DQS.• Every data signal between MD and DQM should be length matched to DQS.• Every data signal between MD and DQM should be length matched to DQS.• Every data signal between MD and DQM should be length matched to DQS.There is only length matching required within each byte lane. There is no signal length matchingrequired outside the byte lane. For example, any signal within MD need not be length matchedto DQS.Total length of each branching in MD/DQM = Total Length of the corresponding DQS +/-0.100"Total length of MD/DQM (TL2A+TL3A) = Total length of DQS (TL2A+TL3A) +/- 0.1"Total length of MD/DQM (TL2B+TL3B) = Total length of DQS (TL2B+TL3B) +/- 0.1"Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 72April 6, 2009, Released