PXA3xx Design Guide - Marvell

DDR Memory Interface (EMPI Bus)EMPI Layout NotesTable 21:Command and Control Signals Routing Recommendations for x32 - 1 DeviceTraceMaxLengthTrace WidthSpacing between this Signal traceand any other Signal traceLayerTL1 (Breakout) 0.4” 3 mils 3 mils HDITL2 0.9” 4 mils 4 mils Buried Micro StripTL3 0.4” 3 mils 3 mils HDI• Recommended maximum via count, including breakout via = 8• Total length of (TL1+TL2+TL3) Max = 1.7"• Refer to matching rules for length matching requirement between CMD and SDCLK.10.4.2.3 Length Matching between SDCLK and CMD for x32 - 1 Device• Total length of CMD/Control = Total Length of SDCLK +/- 0.12"• Total length = TL1+TL2+TL3.10.4.3 Routing Recommendations for x32 - 2 (x16) Devices(PXA32x only)Figure 20: Signal: MD, DQMTable 22:MD and DQM Signals Routing Recommendations for x32 - 2 (x16) devicesTraceMaxLengthTrace WidthSpacing between this Signal traceand any other Signal traceLayerTL1 (Breakout) 0.3” 3 mils 3 mils HDITL2A and TL2B 0.7” 4 mils 4 mils Buried Micro StripTL3A and TL3B 0.2” 3 mils 3 mils HDI• Recommended maximum via count, including breakout via = 8• Total length of (TL1+TL2A+TL3A) Max = 1.1" and• Total length of (TL1+TL2B+TL3B) Max = 1.1"• Length Matching within MD (applies for all 32 MD signals and 4 DQM signals)Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 71