PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign GuideTable 87:Signals to Monitor During Bring-up of the PXA3xx Processor Family (Continued) Signal Name Pin Connection DetailsTESTCLKTied Low for normaloperationTest ClockReserved for manufacturing test. Must be grounded for normaloperation.Memory Controller SignalsnCSDQMChip select signals formemory devicesCorrespondsDQM0 –> MDDQM1 –> MDPXA32x only:DQM3 –> MDDQM2 –> MDChip select 0, 1, 2, 3• SDRAM DQM data byte mask control for data bytes 1 and -0PXA32x only:• SDRAM DQM data byte mask control for data bytes 3 and 2nSDRAS Output SDRAM RASConnect to the row address strobe (RAS) pins for all banks ofSDRAM.nSDCAS CAS for SDRAM SDRAM CASConnect to the column address strobe (CAS) pins for all banks ofSDRAM.SDCKE Output SDRAM clock enableThe signal is de-asserted during sleep. SDCKE1 is alwaysde-asserted upon reset. The memory controller provides controlregister bits for deassertion.DF_SCLK_ESDCLK0,SDCLK1RD/nWRSynchronous FlashOnlySDRAM partition pair0/1TransceiversDirectional SignalSynchronous static memory clocksDDR SDRAM memory clocksSpecial care must be taken when the RD/nWR signal is used withexternal transceivers during any reset mode and the powermodes (idle, standby, sleep, and deep sleep). A problem occurswhen the last transaction is a read (RnW indicates a read), butthe PXA3xx processor family drives the data bus to keep the datafrom floating.A.3 PCB Layout ChecklistTable 88:ItemsThe information in Table 88 is intended for use by those responsible for starting or reviewing a PCBlayout for the PXA3xx processor family.Layout ChecklistRoute DDR memory signals as described in Section 10.4, EMPI Layout Notes .Design for power measurements, if possible.If there is any chance the signal might need to be accessed, bring the signal out to a 0 ohm resistor or a test point.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 212April 6, 2009, Released