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PXA3xx Design Guide - Marvell

PXA3xx Design Guide - Marvell

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<strong>PXA3xx</strong> Processor Family<strong>Design</strong> <strong>Guide</strong>Figure 15: Six Layer Board Stack Up ExampleLAYER 1 HDI 90 Ohms +/- 15%LAYER 2 BMS 60 Ohms +/- 15%LAYER 3 Reference Plane (Power or Ground)LAYER 4 Reference Plane (Power or Ground)LAYER 5 BMS 60 Ohms +/- 15%LAYER 6 HDI 90 Ohms +/- 15%10.4.2 Routing Recommendations for x32 - 1 Device (PXA32x only)Figure 16: Signal: MD, DQMTable 18:MD and DQM Signals Routing Recommendations for x32 - 1 DeviceTraceMaxLengthTrace WidthSpacing between this Signal traceand any other Signal traceLayerTL1 (Breakout) 0.3” 3 mils 3 mils HDITL2 0.6” 4 mils 4 mils Buried MicroStripTL3 0.3” 3 mils 3 mils HDI• Recommended maximum via count, including breakout via = 6Doc. No. MV-S301368-00 Rev. A Copyright © 2009 <strong>Marvell</strong>Page 68April 6, 2009, Released

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