PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 17:SignalNamePXA30x DDR SDRAM I/O Signals (Continued)Direction Polarity DescriptionDQM Output Active High Data byte mask control for external SDRAM.DQM corresponds to MDDQM corresponds to MDDQM corresponds to MD (PXA32x Processor Only)DQM corresponds to MD (PXA32x Processor Only)0 = Do not mask out corresponding byte1 = Mask out corresponding byteDQS Bidirectional N/A DDR Strobe for DDR SDRAM. On reads from DRAM used by controller tolatch data. On writes to DRAM used by DDR DRAM to latch data. Datalatched on both rising and falling clock edges.DQM corresponds to MDDQM corresponds to MDDQM corresponds to MD (PXA32x Processor Only)DQM corresponds to MD (PXA32x Processor Only)SDCLK Output N/A Differential output clock for DDRSDCLK 0 degree phase clock for DDRSDCLK 180 degree phase clock for DDRnSDCS Output Active Low Chip selects for dynamic memory controller. All memory connected to achip select must be either stacked memory or external memory.External/stacked memory on same chip select is not supported.nSDCS DDR Chip Select OnenSDCS DDR Chip Select TwoSDCKE Output Active High Output clock enable signals for external memory. SDCKE is for alldynamic memory chip selects.NOTE: The same clock enable is used for both Chip Selects.nSDRAS Output Active Low Row address strobe for DMCnSDCAS Output Active Low Column address strobe for dynamic memory controllernSDWE Output Active Low Write enable for dynamic memory controllerRCOMP_DDR Output — Resistive compensation10.3 Block DiagramSee Figure 13 and Figure 14 for illustrations of how the PXA3xx processor family memory controllersignals are used to interface DDR SDRAM.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 64April 6, 2009, Released
DDR Memory Interface (EMPI Bus)Block DiagramFigure 13: PXA30x and PXA31x EMPI Memory Configurationx16 DDR SDRAMCK, nCK, CKEnCSnWE, RAS, CASBA1, BA0A, A10DQMDQSDSDCLK0, SDCLK1, SDCKEnSDCS0 or nSDCS1nSDWE, nSDRAS, nSDCASMAMA, SDMA10DQMDQSMDRCOMP_DDRExternal Memory Pin Interface (EMPI)PXA300 orPXA310ProcessorDynamicMemoryController40.2 ohm1% 100mWPossible Chip Select Combinations1 – x16 DDR SDRAM deviceCopyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 65
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