PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign GuideFigure 1:1+6+1 Microvia PCB StackupExternal Sig. Layers1 and 8 50% Copper¼ oz (9um) + plating.102mm (4 mil)μvia copperplatedResin Coated Copper0.070mm2.8 milsInternal Layers2 thru 7 CopperPours 70%Copper½ oz (18um)0.13 mm (5.12 mils) FR40.13 mm (5.12 mils) FR40.13 mm (5.12 mils) FR40.13 mm (5.12 mils) FR4.8-1.0mm(35 +/-3) mils0.13 mm (5.12 mils) FR40.070mm 2.8 milsResin Coated CopperFor the microvia in pad, design the microvia using RCC (resin-coated copper) surface-mountcapture pads.Follow the recommendations for meshing:• For internal layers: 70% cu = 50 mil (1.27mm) pitch with 14.6 mil (.37mm) trace width• For external layers: 50% cu = 50 mil (1.27mm) pitch with 22.6 mil (.57mm) trace widthFollow the recommendations for surface finish and requirements for physical testing:• Surface finish OSP• Use Organic Solder Preservatives (OSP) Entek 106A• Ensure that land pads are as flat as possible (no HASL)• Be aware that industry-wide problems with black pad on ENIG (electroless Ni, Immersion Au)render results useless• Physical testing of PCBs• Moving point probe damages pads that affect mechanical testing results. Therefore, do notperform physical tests of PCBsFigure 2 indicates one possible solution to a single power plane implementation of a power plane ona PCB. Exact implementation depends on system configuration, typical operation, and peripheralvoltage choices. Ensure that all systems—regardless of how many power planes areimplemented—account for maximum current requirements. It is recommended to use two powerplanes. One should be a continuous plane assigned to VCC_APPS. The second plane should bedivided between memory and peripheral I/O.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 22April 6, 2009, Released