PXA3xx Design Guide - Marvell

5 One-Wire Interface5.1 Overview5.2 SignalsThe 1-Wire interface controller is designed to receive and transmit 1-Wire bus data and providescomplete control of the 1-Wire bus through eight-bit commands. The processor loads commands,reads and writes data, and sets interrupt control through five registers. All of the 1-Wire bus timingand control are generated within the 1-Wire interface controller after the host loads a command ordata. When bus activity has generated a response that the CPU needs to receive, the 1-Wire mastersets a status bit and, if enabled, generates an interrupt to the CPU.The operation of the 1-Wire bus is described in detail in the Book of iButton Standards. Refer to thisdocument for details on specific slave implementations.See Table 12 for the description of the 1-Wire bus interface unit signal.Table 12:1-Wire Signal DescriptionSignal Name Input/Output DescriptionONE_WIRE Bidirectional This open-drain signal is the 1-Wire bidirectional data bus. 1-Wire slavedevices are connected to this pin. This pin must be pulled high by anexternal resistor, nominally 5 K ohms.The 1-Wire bus serial operation uses an open-drain, wired-AND bus structure that allows multipledevices to drive the bus lines and to communicate status on events such as arbitration, wait states,and error conditions.5.2.1 1-Wire ConnectionSee Figure 7 for illustration of the schematic showing the connection of the 1-Wire interface to aniButton (a 1-Wire slave device).Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 47