PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 10: JTAG Block DiagramTDIInstructionRegisterBoundary Scan RegisterTMSTCKnTRSTTAPControllerBypass RegisterTDODevice ID RegisterData Specific RegistersControl and Clock Signals9.4 Signal DescriptionsThe JTAG interface is controlled through five dedicated TAP pins: TDI, TMS, TCK, nTRST, andTDO. These pins are described in Table 16.Table 16:TAP Controller Pin DefinitionsName Type DescriptionTCK Input Clock input for the TAP controller, Instruction register, and test data registers. Limited to3.25 MHz maximum frequency for Boundary Scan Register, and 13 MHz for all otherregisters. There is no minimum.TMS Input Controls operation of the TAP controller. TMS is sampled on the rising edge of TCK. TheTMS input is pulled high when not being driven.TDI Input Serial data input to the instruction and test data registers. Data at TDI is sampled on therising edge of TCK. TDI is pulled high by an internal pull-up resistor when not being driven.TDO Output Serial data output. Data at TDO is clocked out on the falling edge of TCK. It provides aninactive (high-Z) state during non-shift operations to support parallel connection of TDOoutputs at the board or module level.nTRST Input Provides asynchronous initialization of the JTAG test logic. Assertion of this pin puts theTAP controller in the TEST_Logic_Reset state. An external source must drive nTRST eitherbefore or at the same time as the hardware nRESET pin for correct TAP controller anddevice operation. The nTRST input is pulled high by an internal pull-up resistor when notbeing driven.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 58April 6, 2009, Released
9.5 JTAG Board ConnectionFigure 11 shows the necessary connections to a 20-pin, 100-mil JTAG-keyed connector.Figure 11: PCB JTAG ConnectionVCC_BBATVCC_BBAT10 K *10 K12nTRSTnTRST34TDI56TMS78PXA3xxProcessorTCK911JTAG1012TDO1314nRESETnSRST15161718192010 KExternal PMIC or resetcircuitRESET OUT* 10K Pullup on nSRST is not needed if there isanother pullup on the Main System RESET#.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 59
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PXA3xx Design Guide - Marvell

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