PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 87: PWM Block Diagram For Applications Requiring a FilterPXA3xxProcessorPWM_OUTxLow PassorBand PassFilterPeripheralUsingPWM25.4 Layout NotesThe maximum switching frequency of the PWM signals is approximately 1.6 MHz. For best results,adhere to all GPIO layout recommendations.A typical use for a PWM output is the contrast control for LCD panels. In this situation, the panelbacklight inverter is a large source of noise. To ensure that the noise is not induced into the contrastcontrol or the processor, follow all recommendations for shielding the inverter and separating theinverter from the contrast control line (PWM output).Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 194April 6, 2009, Released
26 USIM Controller InterfaceThis section describes interface guidelines for the universal subscriber identity module (USIM) of thePXA3xx processor family.26.1 Overview26.2 SignalsThe USIM controller is an interface for a GSM mobile handset. The USIM interface supportscommunication with SmartCards as specified in ISO standard 7816-3 and technical specification 3GTS 31.101 of the 3rd Generation Partnership Project.SmartCards are used in many applications and the GSM network USIM card is only one of thoseapplications. SmartCards usually consist of a CPU, flash memory, and a serial communicationinterface device similar to the one described in this section. More sophisticated cards contain a PLLfor frequency enhancement. Encryption accelerators also exist in a SmartCard as many applicationsare security-oriented. In all SmartCard applications, the physical layer and data link layer areidentical, so the USIM module can serve both layers as well.The USIM interface is composed of eight major components:• Registers• Card interface• Receive FIFO (RXFIFO)• Transmit FIFO (TXFIFO)• Receiver• Transmitter• Clock generator• Baud-rate generatorThe transmitter converts data transferred to its TXFIFO to a serial output as specified by thestandard. The receiver performs the reverse action and stores data taken from its RXFIFO. EachFIFO holds up to 16 bytes. The RXFIFO also holds a parity-error indicator for each byte.Transforming byte convention (inverse to direct and vice-versa) is performed when the byte exits theFIFOs; that is, the FIFO output is either inverted or left as is, according to the session convention. Inthis manner, the program does not have to perform a format inversion before character receipt.Receiver, transmitter, and baud-rate generator blocks are clocked by an internal clock generated inthe clock generator. This unit also generates the card clock. Both receiver and transmitter baud ratesare controlled by the baud-rate generator. Software controls the session with the card by updatingthe USIM registers. All signals going to the USIM card are processed in the card interface block asshown in Figure 88.This section describes the PXA3xx processor family USIM interface I/O signals. See Figure 88 foran illustration showing connectivity between the PXA3xx processor family and an external USIMcard.26.2.1 PXA3xx Processor Family USIM Interface SignalsSee Table 82 for the list of all of the PXA3xx processor family USIM interface signals.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 195
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PXA3xx Design Guide - Marvell

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