PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign Guide18.4 Layout NotesRefer to the PHY data sheet for additional guidelines and layout notes. Some of the PHY devicesmay have strict requirements which must be adhered too.DPlus and DMinus are differential pair signals. Follow these layout guidelines:• Route the signals close to each other as parallel traces on the PCB.• Route the differential pair with trace width and spacing needed to achieve 90 ohms differentialimpedance. Deviations will normally occur due to package breakout and routing to connectorpins. Keep the amount and length of width/spacing deviations to a minimum.• Route high-speed USB signals using a minimum of vias and corners. When a corner isnecessary, use two 45 degree turns or an arc instead of a single 90 degree turn. This reducessignal reflections and impedance discontinuities.• Do not route USB traces under crystals, oscillators, magnetic devices or IC’s that use and/orduplicate clocks.• Avoid stubs on USB signals as the stubs will cause reflections and affect signal quality.• Route USB signals over continuous planes (VCC or GND) with no interruptions. Avoid crossingplane splits if possible.• Minimize the length of parallel running signals, especially clocks to avoid crosstalk. Minimumsuggested spacing to clocks is 50 mils. Minimum suggested spacing to other signals is 20 mils.• Match the trace lengths for USB high speed signals as closely as possible (within ±0.150 inches(3.81 mm)).Refer to Figure 67 and the following sections for general routing guidelines.Figure 67: General Signal Routing Diagram - Applicable to All SignalsPXA30x, MonahansPXA32xT1-MohanansBreakoutPXA30x, PXA32xT3-PhyBreakoutUSB 2.0TransceiverT2-PrincipalRoutingCompatible USB UTMI (Universal Transceiver Macrocell Interface) transceivers are: SMSCUSB3280, Cypress CY7C68000.18.4.1 Signal Routing Guidelines18.4.1.1 Data Signals (Data 0 through Data 7)*T1- Microstrip construction, 50 Ω