PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign Guide• Ensure TDI and TMS pins and EXT_WAKEUP are pulled high or remain floating.• Ensure the USB OTG differential inputs (USBOTG_P and USBOTG_N) are driven high orremain floating with no impact to OTG pins.3.4 Achieve Minimum Power Usage During S2/D3/C4The following are methods used for achieving lowest power consumption during S2/D3/C4 powermode:• If none of the contents of internal SRAM are to be retained, ground VCC_APPS andVCC_SRAM to attain the lowest power consumption and validate the design. If contents withininternal SRAM are to be retained, only ground VCC_APPS to attain the lowest powerconsumption.• Set all other power domains to their minimum possible voltage allowable by the systemconfiguration. This minimum possible voltage depends on the peripherals connected to thePXA3xx processor family. All voltages must comply with the voltage requirements of thePXA3xx processor family. Refer to the Marvell ® PXA30x, PXA31x, and PXA32x ProcessorElectrical, Mechanical, and Thermal Specification for more information.• Ensure AD3R[AD3_L2] = 0b0. This verifies that the L2 cache is in the D4 state. This step isoptional.• To verify that the PXA3xx processor family PMU is in the S2 state use JTAG to check thatPSR[SS2S] = 0b1. This step is optional.• To verify that the applications subsystem is in the D3 state use JTAG to check that ASCR[D3S]= 0b1. This step is optional.• Configure AD3R[AD3_Rx] appropriately to retain state in the internal SRAM. Write 0b1 for eachbank of internal SRAM that will retain data during S2/D3/C4 and write 0b0 to all other banks.• Clear PCFR[PUDH]. This disables the pull-up and pull-down registers for nGPIO_RESET,EXT_WAKEUP, PWR_SCL, and PWR_SDA.• Configure OSCC[TENS2] appropriately. This setting is system dependent. Refer to the Marvell ®PXA30x, PXA31x, and PXA32x Processor Electrical, Mechanical, and Thermal Specification forthe proper configuration state for the pins during S2/D3/C4. Configure the multi-function pins ofthe PXA3xx processor family using the MFPRx registers. If a pin is configured as an input andnot used as a wake-up source it should be driven low from an external source.• Ensure TDI and TMS pins and EXT_WAKEUP are pulled high or remain floating.• Ensure the USB OTG differential inputs (USBOTG_P and USBOTG_N) are driven high orremain floating with no impact to OTG pins.3.5 Achieve Minimum Power Usage During S0/D2/C2(PXA30x and PXA31x only)The following are methods used to achieve lowest power consumption during S0/D2/C2 powermode:• Set VCC_APPS and VCC_CORE to the minimum allowable voltage for S0/D2/C2 as defined inthe Marvell ® PXA30x and PXA31x Processor Electrical, Mechanical, and Thermal Specification.• Set all other power domains to their minimum possible voltage allowable by the systemconfiguration. This is dependent upon the peripherals connected to the PXA30x and PXA31xprocessor. All voltages must comply with the voltage requirements of the PXA3xx processorfamily. Refer to the Marvell ® PXA30x and PXA31x Processor Electrical, Mechanical, andThermal Specification for more information.• Clear PCFR[PUDH]. This disables the pull-up and pull-down registers for nGPIO_RESET,EXT_WAKEUP, PWR_SCL and PWR_SDA.• Configure AD2R[AD2_Rx] appropriately to retain state in the internal SRAM. Write 0b1 for eachbank of internal SRAM that will retain data during S0/D2/C4 and write 0b0 to all other banks.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 32April 6, 2009, Released
• Configure OSCC[TENS0] appropriately. This setting is system dependent.• To verify that the applications subsystem is in the D2 state use JTAG to check that ASCR[D2S]= 0b1. This step is optional.• Ensure AD2R[AD2_L2] = 0b0. This verifies that the L2 cache is in the D2 state. This step isoptional.• Ensure TDI and TMS pins and EXT_WAKEUP are pulled high or remain floating.• Ensure the USB OTG differential inputs (USBOTG_P and USBOTG_N) are driven high orremain floating with no impact to OTG pins.3.6 Achieve Minimum Power Usage During S0/D1/C2(PXA30x and PXA31x only)The following methods are used to achieve lowest power consumption during S0/D1/C2 powermode:• Set VCC_APPS and VCC_CORE to the minimum allowable voltage for S0/D1/C2 as defined inthe Marvell ® PXA30x and PXA31x Processor Electrical, Mechanical, and Thermal Specification.• Set all other power domains to their minimum possible voltage allowable by the systemconfiguration. This is dependent upon the peripherals connected to the PXA3xx processorfamily. All voltages must comply with the voltage requirements of the PXA30x and PXA31xprocessor. Refer to the Marvell ® PXA30x and PXA31x Processor Electrical, Mechanical, andThermal Specification for more information.• Clear PCFR[PUDH]. This disables the pull-up and pull-down registers for nGPIO_RESET,EXT_WAKEUP, PWR_SCL, and PWR_SDA.• Configure AD2R[AD2_Rx] appropriately for the LCD buffer in the internal SRAM. Write 0b1 foreach bank of internal SRAM that contains LCD frame buffer data and write 0b0 to all otherbanks.• Configure OSCC[TENS0] appropriately. This setting is system dependent.• To verify that the applications subsystem is in the D1 state use JTAG to verify that ASCR[D1S] =0b1. This step is optional.• Ensure AD1R[AD1_L2] = 0b0. This verifies that the L2 cache is in the D1 state. This step isoptional.• Ensure TDI and TMS pins and EXT_WAKEUP are pulled high or remain floating.• Ensure the USB OTG differential inputs (USBOTG_P and USBOTG_N) are driven high orremain floating with no impact to OTG pins.3.7 Achieve Minimum Power Usage During S0/D0CSIdleThe following are methods used to achieve lowest power consumption during S0/D0CS Idle powermode:• Set VCC_APPS and VCC_CORE to the minimum allowable voltage for S0/D0CS Idle asdefined in the Marvell ® PXA30x, PXA31x, and PXA32x Processor Electrical, Mechanical, andThermal Specification.• Set all other power domains to their minimum possible voltage allowable by the systemconfiguration. This is dependent upon the peripherals connected to the PXA3xx processorfamily. All voltages must comply with the voltage requirements of the PXA3xx processor family.Refer to the Marvell ® PXA30x, PXA31x, and PXA32x Processor Electrical, Mechanical, andThermal Specification for more information.• Clear PCFR[PUDH]. This disables the pull-up and pull-down registers for nGPIO_RESET,EXT_WAKEUP, PWR_SCL, and PWR_SDA.• Configure OSCC[TENS0] appropriately. This setting is system dependent.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 33
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PXA3xx Design Guide - Marvell

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