PXA3xx Design Guide - Marvell

More documents

Recommendations

Info

PXA3xx Processor FamilyDesign GuideTable 67:USB Host Controller Interface Signals Summary (Continued)Signal Name Ball Name Type DescriptionUSBOTG_P USBOTG_P Analog USB Full Speed Host/Client/OTG Port 2 Positive Line — this isthe positive pin of the differential pair that connects to the USB fullspeed host, or the USB full speed client, or the USB OTG interfacefor Port 2.USBOTG_N USBOTG_N Analog USB Full Speed Host/Client/OTG Port 2 Negative Line — this isthe negative pin of the differential pair that connects to the USB FullSpeed Host, or the USB Full Speed Client, or the USB OTGinterface for Port 2.USBHPEN2GPIO103(PXA30xprocessor)OutputUSB Full Speed Host Port 2 Power Control — controls power tothe USB Host Port 2. This signal is muxed with USB_P2_8 butdepends on the value of UP2OCR[SEOS]. Refer to The UniversalSerial Bus Client Controller chapter of the Marvell ® PXA30x,PXA31x, and PXA32x Processor Serial Controller ConfigurationDevelopers Manual, Vol. IV Developers Manual: Serial ControllerConfiguration for more information.USB Full Speed Single-Ended Signals - Port 2 Host/Client and OTGUSB_P2_1GPIO101(PXA30xprocessor)GPIO36(PXA31xprocessor)Bidirectional USB Full Speed Host/Client and OTG Port 2 RCV/INT/SRP —This signal is the receive data from an external USB transceiver forPort 2. When configured for an external OTG transceiver this signalis an interrupt input. When configured for an external OTG powercontroller and the internal transceiver, this signal is the SRP detectinput.USB_P2_2GPIO99 orGPIO100(PXA30xprocessor)GPIO30(PXA31xprocessor)BidirectionalUSB Full Speed Host/Client and OTG Port 2 OE/Valid—Thissignal connects to the OE signal of an external USB transceiver forUSB Port 2. This signal connects to the session valid output of anexternal OTG power controller.USB_P2_3GPIO104(PXA30xprocessor)GPIO35(PXA31xprocessor)BidirectionalUSB Full Speed Host/Client and OTG Port 2 RXD-/SV—Thissignal is the receive negative data line from an external USBtransceiver for Port 2. For an external OTG power controller, thissignal is the session valid status input.USB_P2_4USB_P2_5GPIO102(PXA30xprocessor)GPIO32(PXA31xprocessor)GPIO105(PXA30xprocessor)GPIO34(PXA31xprocessor)Bidirectional USB Full Speed Host/Client and OTG Port 2TXD-/SE0_VM/SRP—This signal is the transmit negative data lineto an external USB transceiver for Port 2. For an external OTGtransceiver, this signal is the SE0_VM bidirectional data line. For anexternal OTG power controller this signal is the SRP enable controloutput.Bidirectional USB Full Speed Host/Client and OTG Port 2RXD+/DAT_VP/VALID40—This signal is the receive positive dataline from an external USB transceiver for Port 2. For an externalOTG transceiver, this signal is the DAT_VP bidirectional data line.For an external OTG power controller this signal is the 4.0 V Vbusvalid status input.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 164April 6, 2009, Released
Table 67:USB Host Controller Interface Signals Summary (Continued)Signal Name Ball Name Type DescriptionUSB_P2_6GPIO99 orGPIO100(PXA30xprocessor)GPIO31(PXA31xprocessor)BidirectionalUSB Full Speed Host/Client and OTG Port 2 TXD+ —This signalis the positive transmit data line for an external USB transceiver forPort 2PUSB_P2_7USB_P2_8GPIO106(PXA30xprocessor)GPIO103(PXA30xprocessor)Bidirectional USB Full Speed Host/Client and OTG Port 2Speed/OTGID—Speed select signal for USB Port 2 whenconfigured for an external USB transceiver. Provides the OTG IDconfiguration using the internal transceiver.Input USB Full Speed Host/Client and OTG Port 2Suspend—Suspend enable for USB Port 2 when configured for anexternal USB OTG transceiver.USB Full Speed Single-Ended Signals - Port 3 HostUSB_P3_1GPIO77(PXA3xxprocessorfamily)BidirectionalUSB Full Speed Host Port 3 RCV—receive data signal thatconnects to an external transceiver or the transceiver interface of aUSB device controller as defined by the CFG bits in the USB Port 3Output Control register (UP3OCR).USB_P3_2GPIO78(PXA3xxprocessorfamily)BidirectionalUSB Full Speed Host Port 3 OE—output enable signal whichconnects to an external transceiver or the transceiver interface of aUSB device controller as defined by the CFG bits in the USB Port 3Output Control register (UP3OCR).USB_P3_3GPIO79(PXA3xxprocessorfamily)BidirectionalUSB Full Speed Host Port 3 RXD- —receive data (-) signal whichconnects to an external transceiver or the transceiver interface of aUSB device controller as defined by the CFG bits in the USB Port 3Output Control register (UP3OCR).USB_P3_4GPIO80(PXA3xxprocessorfamily)BidirectionalUSB Full Speed Host Port 3 TXD- —transmit data (-) signal whichconnects to an external transceiver or the transceiver interface of aUSB device controller as defined by the CFG bits in the USB Port 3Output Control register (UP3OCR).USB_P3_5GPIO81(PXA3xxprocessorfamily)BidirectionalUSB Full Speed Host Port 3 RXD+ —receive data (+) signal whichconnects to an external transceiver or the transceiver interface of aUSB device controller as defined by the CFG bits in the USB Port 3Output Control register (UP3OCR).USB_P3_6GPIO82(PXA3xxprocessorfamily)BidirectionalUSB Full Speed Host Port 3 TXD+ —transmit data (+) signalwhich connects to an external transceiver or the transceiverinterface of a USB device controller as defined by the CFG bits inthe USB Port 3 Output Control register (UP3OCR).20.3 Block DiagramsHost controller Port 1 is used only with a differential connections. Host controller Port 2 is used witheither a differential connection or a single-ended connection. Host controller Port 3 is used only witha single-ended connection.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 165
Page 5 and 6:
10.2 Signals ......................
Page 7 and 8:
17.2 Signals ......................
Page 9 and 10:
26.2 Signals ......................
Page 11 and 12:
Copyright © 2009 MarvellDoc. No. M
Page 13 and 14:
Figure 42: SPI Protocol Interface B
Page 15:
TablesTable 1: How Design Guide Cha
Page 18 and 19:
PXA3xx Processor FamilyDesign Guide
Page 20 and 21:
Page 22 and 23:
Page 24 and 25:
Page 26 and 27:
Page 28 and 29:
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
Page 40 and 41:
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 62 and 63:
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Page 110 and 111:
Page 112 and 113:
Page 114 and 115: PXA3xx Processor FamilyDesign Guide
Page 214 and 215:
show all

PXA3xx Design Guide - Marvell

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?