PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 62: Connection to External OTG TransceiverUSB HostController123Transmit enableUSB_P2_4USB_P2_5USB DeviceControllerD+/D-TransmitenableUP2OCR[EXSUS]UP2OCR[EXSP]Ext. Trans. InterruptUP2OCR[SEOS]USB_P2_2USB_P2_8USB_P2_7OE_Tp_Int_NSuspend EnableSpeed ControlIDExternal OTGTransceiverDat_VPSE0_VMVbusD +D -InterruptVbusD +D -USB_P2_1PXA30x ProcessorOTG ID17.4.5 Interface to External Charge Pump Device (OTG)In addition to interface options to internal and external OTG transceivers, the UDC provides controloutputs and interrupt inputs to drive and monitor an external charge pump device. In this mode, D+and D- signals of the USB are output using the on-chip OTG transceiver and the Vbus interface isprovided by an external charge pump device. In this mode, the HXS bit in “USB Port 2 OutputControl Register (UP2OCR)” uses the control multiplexors to select between the UDC and D+, D-,and transmit-enable signals of the USB host controller. These signals are output through the USBhost controller port 2 transceiver.In addition, to enable the driving of Vbus and the driving of pulses on Vbus, the “USB Port 2 OutputControl Register (UP2OCR)” provides (1) the charge pump Vbus-enable (CPVEN) control-output bitand (2) the charge pump Vbus pulse-enable (CPVPE) control-output bit.Additionally, “USB Port 2 Output Control Register (UP2OCR)” provides the following inputs tointerface to the external charge pump device:• Vbus valid 4.0• Vbus valid 4.4• Session valid• Session-request protocol (SRP) detected interruptSee Figure 63 for illustration of the PXA30x processor or PXA32x processor OTG connections to anexternal charge pump device.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 146April 6, 2009, Released
Figure 63: Connection to External OTG Charge PumpUSB HostController123USB Host Port2 TransceiverOEUSBOTG_P / USBOTG_ND+ D-USB DeviceControllerD+,D-UP2OCR[HXS]UP2OCR[HXOE]USB_P2_4USB_P2_8Vbus EnableVbus PulsingEnable for SRPVbusVbus valid 4.0 VVbus valid 4.4 VSRP DetectSession ValidExternal Charge PumpVbusTo USBUP2OCR[CPVEN]UP2OCR[CPVPE]USB_P2_5Vbus Valid 4.0 VVbus Valid 4.4 VSRP DetectUSB_P2_3Session ValidUP2OCR[SE0S]USB_P2_1OTG IDUSB_P2_2PXA300 ProcessorUSB_P2_7OTG ID17.4.6 OTG IDThe UDC provides OTG ID interface support through USB_P2_7 on GPIO[104]. The UDC provides“USB Port 2 Output Control Register (UP2OCR)” ID output enable (IDEN) to enable the output forOTG ID reading and the OTG ID interrupt input to detect changes in the OTG ID signal. When IDENis set to 1, it enables the output of GPIO[104] and driven high with a weak output driver. Therefore,when the OTG ID pin on the USB connector is connected to a 100 KΩ resistor, the OTG ID inputresults in 1; when the OTG ID pin is connected to a 10 Ω resistor to ground, the GPIO[104] outputdriver is unable to drive OTG ID to a 1, resulting in the OTG ID input being a 0. See Figure 64 forillustration of the PXA30x processor or PXA32x processor interface to OTG ID.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 147
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Copyright © 2009 MarvellDoc. No. M
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Figure 42: SPI Protocol Interface B
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TablesTable 1: How Design Guide Cha
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PXA3xx Processor FamilyDesign Guide
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PXA3xx Design Guide - Marvell

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