PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 84:I 2 C Signal Description (Continued)Signal Name Input/Output DescriptionPWR_SCL Bidirectional Serial clock for Power I 2 C controller.NOTE: For 3.3 V or less on I 2 C controller, 1.2 KΩ pull-up resistor must beused.The I 2 C bus serial operation uses an open-drain, wired-AND bus structure that allows multipledevices to drive the bus lines and to communicate status on events such as arbitration, wait states,and error conditions. For example, when a master drives the SCL during a data transfer, it transfersa bit every time the clock is high. When the slave is unable to accept or drive data at the rate that themaster is requesting, the slave holds SCL low between the high states to insert a wait interval. Themaster clock is only altered by a slow slave peripheral keeping the clock line low or by anothermaster during arbitration.The I 2 C bus allows design of a multi-master system, meaning more than one device can initiate datatransfers at the same time. To support this feature, the I 2 C bus arbitration relies on the wired-ANDconnection of all I 2 C interfaces to the I 2 C bus. Two masters can drive the bus simultaneously,provided they are driving identical data. The first master to drive SDA high while another masterdrives SDA low loses the arbitration. The SCL consists of a synchronized combination of clocksgenerated by the masters using the wired-AND connection to the SCL.27.3 Layout NotesThe maximum switching frequency of the I 2 C signals is 400 kHz. Therefore, layout and routingconsiderations are not stringent. However, for best results, adhere to common layoutrecommendations.Separate the physical routing of the data and clock signals and ensure that lines are not routed nearother potential noise sources, such as switching regulators or signals with high switchingfrequencies.NoteBe sure and connect all I 2 C signals to the correct voltage levels using 1.2 KΩ pull-upresistors.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 202April 6, 2009, Released
ADesign ChecklistThis Appendix is a design-review checklist for systems using the PXA3xx processor family prior tolayout, during layout, during bring-up, and software optimization. It is a good idea to consult thissection if any problems occur while bringing up the PXA3xx processor family system for the firsttime. Each table within this section has a column reserved for reviewing designers to verify the lineitem has been checked.A.1 Schematic ChecklistTable 85 briefly describes requirements to add in schematics reviews. Refer to the various sectionswithin this Design Guide for more information about these requirements.Table 85:PXA3xx Processor Family Schematic Checklist Signal Name Category DetailsPower DomainsAll VCC powerdomainsAll power domainconnectionsVerify properdecouplingVerify connectionsCheck all VCC power domains for proper decoupling – both Bulkand Edge decoupling capacitors. Recommend using 0402, 1.0µF, X5R, low inductance, low ESR capacitors. See Section 2.2,Power Supply Decoupling RequirementsPower Distribution:• Verify each power domain gets proper power/voltage(including power-up sequencing)• Verify each chip (DDR, SRAM, FLASH, companion chips,etc.) has proper power/voltage• Analog sections may need their power filtered if usingcommon regulator• Check for maximum required current and total availablecurrent for each voltage railnBATT_FAULT Weak pull-up Add weak pull-up (50 KΩ) to nBATT_FAULTTest and Reset SignalsTEST Tie to GND Required on all systems during normal operation. Reserved forfactory testing.TESTCLK Tie to GND Required on all systems during normal operation. Reserved forfactory testing.nRESET_OUTClocks and PowerLevel shifter may berequiredDriven high at VCC_BBATT voltage level. Need to level-shiftdown to 1.8 V when used as reset on 1.8 V components.PXTAL_IN,PXTAL_OUT13 MHz crystal only No other discrete components required or recommended. Donot connect load capacitors from either signal to ground.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 203
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Figure 42: SPI Protocol Interface B
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PXA3xx Design Guide - Marvell

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