PXA3xx Design Guide - Marvell

4 Clocks and Power Interface4.1 Overview4.2 SignalsThis section describes design recommendations and requirements for the external clock and powersupply components connected to the PXA3xx processor family.The following sections describe signals required for the clock and power interface.4.2.1 Clock Interface SignalsSee Table 9 for definition of the PXA3xx processor family clock signals as well as reset and wake-upsource signals.Table 9:Clock Manager Pin DefinitionsDevice I/O Type DefinitionPXTAL_IN Analog Input The PXTAL_IN signal can be connected to an external 13 MHz crystal or to anexternal 13 MHz clock source and is the reference clock for internal PLLs.PXTAL_OUT Analog Output The PXTAL_OUT signal can be connected to an external 13 MHz crystal or floatedif an external 13 MHz clock source is used to drive PXTAL_IN.TXTAL_IN Analog Input The TXTAL_IN signal can be connected to an external 32.768 kHz crystal or to anexternal clock source and is distributed to the Timekeeping control system andPower Management Unit (PMU).TXTAL_OUT Analog Output The TXTAL_OUT signal can be connected to an external 32.768 kHz crystal orgrounded when TXTAL_IN is driven by an external oscillator.CLK_POUT Output Processor oscillator clock output for system use.CLK_TOUT Output Timekeeping oscillator clock output for system use.VCTCXO_EN Output VCTCXO_EN output signal is used to enable the processor oscillatorclock source.4.2.2 Power Manager Interface Control SignalsThe PXA3xx processor family has an internal power manager unit (PMU) and a set of I/O signals forcommunicating with an external power management integrated circuit (PMIC). The I/O signals areactive for initial power-up, certain reset events, device on/off events, and transitions between someoperating modes. The PMIC must supply the fault signal, nBATT_FAULT, to communicate the onsetof power supply problems to the PXA3xx processor family.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 35