PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 79: Recommended Layer Stack UpLAYER 1 HDI 90 OhmsLAYER 2 BMS 60 OhmsLAYER 3 Power or Ground FloodLAYER 4 Power or Ground FloodLAYER 5 BMS 60 OhmsLAYER 6 HDI 90 OhmsTable 71:AC ‘97 Signals and Possible Loading ConfigurationsSignals Type 1 Load 2 LoadsAC97_SDATA_OUT Output Yes YesAC97_SYNC Output Yes YesAC97_nACRESET Output Yes YesAC97_SDATA_IN[3:0] Input Yes YesAC97_BITCLK Input Yes YesDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 182April 6, 2009, Released
22.6 Routing Recommendations22.6.1 Topology # 1: SDATA_OUT / SYNC with a Single LoadFigure 80: Topology # 1 - PXA3xx Processor Family SDATA_OUT and SYNC to a Single AC ‘97CodecTable 72:Signal: AC97 SDATA_OUT and SYNC (Single Load)Mode Section Maximum Length * Minimum Length1.8 V HDI_1 + BMS + HDI_2 5 inches 0.5 inches3.3 V HDI_1 + BMS + HDI_2 7 inches 0.5 inches• HDI should be used mainly for breakout. Maximum length on HDI_1 or HDI2 is 0.5 inches.• This topology is point-to-point with no stubs.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 183
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Figure 42: SPI Protocol Interface B
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TablesTable 1: How Design Guide Cha
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PXA3xx Processor FamilyDesign Guide
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PXA3xx Design Guide - Marvell

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