PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign GuideTable 59:UTMI Interface Signals Summary (Continued)Signal Name Type Signal DescriptionsUTM_LINESTATE Input UTMI Line State—Connects to the single-ended receiver statussignals. They are asynchronous until a usable CLK is available, thenthey are synchronized to CLK. They directly reflect the current state ofthe DP (LineState[0]) and DM (LineState[1]) signals:D– D+ Description0 0 SE00 1 “J” State1 0 “K” State1 1 SE1U2D_TXVALID Output UTMI Transmit Valid—Indicates that the transmit output data is valid.UTM_TXREADY Input UTMI Transmit Data Ready—If this signal is asserted, the controllerwill have data available for clocking in to the TX Holding register onthe rising edge of UTM_CLK.UTM_RXVALID Input UTMI Receive Data Valid—Indicates that the data bus has valid data.UTM_RXACTIVE Input UTMI Receive Active—Indicates that the receive state machine hasdetected SYNC and is active.U2D_RXERROR Output UTMI Receive Error—Connects to the transceiver error output. Highindicates that a receive error has been detected.U2D_OPMODE Output UTMI Operating Mode—These signals configure the transceiveroperating modes:OPMODE Description0 0 Normal Operation0 1 Non-Driving1 0 Disable Bit Stuffing and NRZI encoding1 1 Reserved18.3 Block DiagramFigure 66 shows the U2D block diagram for the PXA30x or PXA32x processor using the UTMIinterface.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 152April 6, 2009, Released