PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign GuideCarkit mode support requires the ability to multiplex a UART peripheral interface and an audioCODEC over the USB D+ and D- signal pins. The processor UART peripheral interface can be usedfor this function by placing it in Transparent mode. The UART transmit (TxD) and receive (RxD) datapins are multiplexed over the USB D- and D+ pins during carkit UART signaling mode, respectively.The audio codec is an external component to the processor, and its SPKR_L and SPKR_R/MICanalog signals are multiplexed over the USB D- and D+ pins during the carkit audio modes. (Bothmono and stereo audio modes are supported by the carkit standard). Refer to the CEA-936Astandard for more information on this option.UART requirements are:• UART data rate of 9600 kbps• 8-bit• No parity• One stop bit• Assertion high polarityTable 63:Carkit Signal MappingSignal ULPI GPIO PHY DIR DescriptionTxD Data[0] GPIO30 Input UART TxD routed to D- pinRxD Data[1] GPIO31 Output UART RxD routed to D+ pinRESERVED Data[2] GPIO32 Output ReservedINTERRUPT Data[3] GPIO33 Output Active high interrupt19.4 Layout NotesSection 19.4.1, “General Routing Recommendations” describes general routing recommendationsfor the PXA31x processor ULPI interface. Refer to the PHY data sheet and layout notes foradditional guidelines. Some of the PHY devices may have strict requirements which must befollowed.19.4.1 General Routing RecommendationsThe following recommendations are intended for the PXA31x ULPI interface.• Minimum 6-layer board is recommended.• HDI and BMS routes are recommended.• Minimum 1:1 edge-to-edge spacing is recommended for all traces.MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 160April 6, 2009, Released