PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 11:VoltageSupplyPower Domains (Continued)Domain Name and DescriptionVCC_IO4VCC_IO6VCC_DFVCC_CIVCC_LCDVCC_MEMVCC_MSLVCC_CARD1VCC_CARD2VCC_BIASVCC_ULPINOTE: PXA32x onlyFixed supplies for standard CMOS I/Os interfacing to external component I/Os, which are alsopowered from this same supply. The I/Os for external components connected to the correspondingsignals on the PXA32x must be supplied from the same regulator. The VCC_IOx domains must beenabled when SYS_EN is asserted and disabled when SYS_EN is de-asserted.Although separately named, these supplies may be connected together if their voltages are identical.For example, VCC_IO1 and VCC_IO6 both require 1.8 V if these supplies are connected together onthe system PCB.Power to I/Os at Data Flash Interface (DFI). This supply must be enabled when SYS_EN is assertedand disabled when SYS_EN is de-asserted.NOTE: PXA30x and PXA31x processors using the MCP package must have VCC_DF connected to1.8 V. NAND devices connected to the MCP versions are 1.8 V.Power to I/Os of Capture Interface. This supply must be enabled when SYS_EN is asserted anddisabled when SYS_EN is de-asserted.Power for output drivers to LCD panel. Optionally, this domain may be strapped to another I/O supplyat the required voltage if desired. This supply must be enabled when SYS_EN is asserted anddisabled when SYS_EN is de-asserted.Tightly regulated power supply for DDR DRAM memory or companion chip bus I/O. CorrespondingI/Os of the memory components or companion chips must be powered from the same regulator. Thissupply must be enabled when SYS_EN is asserted and disabled when SYS_EN is de-asserted. Thissupply must not be connected to any other PXA3xx processor family power domains.Power for I/Os of a multipurpose fast serial port, which connects to external baseband module orother devices. Corresponding I/Os of the baseband device must be powered from the same regulator.Optionally, this domain may be strapped to another I/O supply at the required voltage if desired. Thissupply must be enabled when SYS_EN is asserted and disabled when SYS_EN is de-asserted.Power for I/Os to an external removable storage or I/O card, including Universal Subscriber IdentityModule (USIM) cards. These may have independent power supplies operating at different voltages.The VCC_CARDx voltage generated by the PMIC is software configurable at settings of 1.8 V, 3.0 Vor 3.3 V or disabled. The software voltage control is implemented using I 2 C commands or the PMICdecodes the PXA3xx processor family UVS0, nUVS1, and nUVS2 outputs. Refer to the ClockControllers and Power Management Chapter in Marvell ® PXA30x, PXA31x, and PXA32x ProcessorsVol. I: System and Timer Configuration Developers Manual for more information.NOTE: 3.3 V is not a voltage supported by USIM cards. However, some alternatefunctions can be configured using the pins powered by VCC_CARD1 and VCC_CARD2. Therefore,these domains can be required to operate at 3.3 V.NOTE: PXA31x Processor onlyInternal SRAM back bias.NOTE: PXA31x Processor onlySupply for USB for standard differential USB digital I/Os interfacing to external components.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 38 April 6, 2009, Released
Table 11:VoltageSupplyVCC_USBPower Domains (Continued)Domain Name and DescriptionNOTE: PXA30x Processor and PXA32x Processor onlyPower for USB for standard differential USB I/Os interfacing to external components,which are also supplied from a fixed 3.3V supply.NOTE:VCC_USB powers the I/O for the USB interfaces. The USB differential signals D+ and D- are outof compliance with the USB specification if VCC_USB falls below 2.8 V.The +5 V VBUS source from USB host controller, which must be available forbus-powered peripherals, must be supplied from an external source like the PMIC. It is not part ofthe PXA3xx processor family silicon.NOTE: PXA31x Processors trusted boot designs must ensure that VCC_MVT, VCC_BG, VCC_PLL and VCC_OSC13Mare connected to a power supply that is capable of 1.9 V and that no other power domains are connected to thispower supply.NoteThe USB 2.0 Client UTMI connection to an external USB 2.0 UTMI PHY is 22 pins.These pins connect to multiple power domains inside the PXA3xx processor family.Since the UTMI interface must be run at 3.3 V, all of the domains the UTMI pins usemust be run at 3.3 V.4.2.2.1 Power Enable (PWR_EN)PWR_EN is an active-high output from the PXA3xx processor family (input to the PMIC), whichenables the low-voltage core and internal SRAM power supplies (VCC_APPS and VCC_SRAM).De-asserting PWR_EN informs the external regulator that the processor is going into S2/D3/C4mode or S3/D4/C4 mode, and that the low-voltage core power supplies are to be shut down.The PMIC turns on the low-voltage supplies in response to a PWR_EN assertion to resume normaloperation. During S2/D3/C4 mode or S3/D4/C4 mode, the power controller must preserve theprevious state of its regulators including the voltage for the core, so that on resumption of corepower, the regulators return to their last known voltage levels.NoteThe low-voltage power supplies (VCC_APPS and VCC_SRAM) can also be controlledvia I 2 C commands. All low-voltage power supplies must be removed before removingany high-voltage power supply.4.2.2.2 System Power Enable (SYS_EN)SYS_EN is an active-high output from the PXA3xx processor family (input to the PMIC), whichenables the system (high-voltage) power supplies. De-asserting SYS_EN informs the power supplythat the PXA3xx processor family is going into S3/D4/C4 mode, and that the high-voltage systempower supplies (VCC_BG, VCC_PLL, VCC_MVT, VCC_OSC13M, VCC_IO1, VCC_IO3, VCC_LCD,VCC_MEM, VCC_CARDx, VCC_MSL, VCC_CI, VCC_DF, and VCC_BIAS, VCC_ULPI) are to beshut down. Assertion and de-assertion of SYS_EN occurs in the correct sequence with PWR_EN orI 2 C commands to ensure the correct sequencing of power supplies when powering on and off thevarious voltage domains. To resume normal operation, the PMIC must first turn on the system I/O(high-voltage) supplies in response to SYS_EN assertion and then turn on the core (low-voltage)supplies in response to PWR_EN assertion or I 2 C commands. The power controller must return allsystem I/O voltages to their pre-S3/D4/C4 mode levels.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 39
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PXA3xx Design Guide - Marvell

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