PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 69:SSP Serial Port I/O Signals (Continued)Name Direction DescriptionSSPSFRM Inout Synchronous Serial Protocol Serial Frame Indicator – SSPSFRM, theserial frame indicator, determines the beginning and the end of aserialized data word. SSPSFRM is generated internally (master mode)or is supplied externally (slave mode) as indicated bySSCR1_1[SFRMDIR].SSPTXD Output Synchronous Serial Protocol Transmit Data – SSPTXD is the transmitdata (serial data out) serialized data line.SSPRXD Input Synchronous Serial Protocol Receive Data – SSPRXD is the receivedata (serial data in) serialized data line.SSPEXTCLK Input Synchronous Serial Protocol External Clock – SSPEXTCLK is anexternal clock that is selected to replace the internal 13 MHz clock.SSPEXTCLK is multiplexed with the SSPSCLKEN alternate function.SSPSCLKEN Input Synchronous Serial Protocol Serial Clock Enable – SSPSCLKEN is anasynchronous external enable for SSPSCLK. SSPSCLKEN ismultiplexed with the SSPEXTCLK alternate function.SSPSCLK2 Inout Synchronous Serial Protocol Serial Clock 2 – SSPSCLK2 is the serial bitclock used to control the timing of a transfer. SSPSCLK2 is generatedinternally (master mode) or is supplied externally (slave mode) asindicated by SSCR1_2[SCLKDIR].SSPSYSCLK2 Output Synchronous Serial Protocol System Clock 2 – SSPSYSCLK2 is one,four, or eight times the SSPSCLK2 value, depending onSSACD_2[SCDX8] and SSACD_2[SCDB].SSPSFRM2 Inout Synchronous Serial Protocol Serial Frame Indicator 2 – SSPSFRM2, theserial frame indicator, determines the beginning and the end of aserialized data word. SSPSFRM2 is generated internally (master mode)or is supplied externally (slave mode) as indicated bySSCR1_2[SFRMDIR].SSPTXD2 Output Synchronous Serial Protocol Transmit Data 2 – SSPTXD2 is the transmitdata (serial data out) serialized data line.SSPRXD2 Input Synchronous Serial Protocol Receive Data 2 – SSPRXD2 is the receivedata (serial data in) serialized data line.SSPEXTCLK2 Input Synchronous Serial Protocol External Clock 2 – SSPEXTCLK2 is anexternal clock that is selected to replace the internal 13 MHz clock.SSPEXTCLK2 is multiplexed with the SSPSCLK2EN alternate function.SSPSCLK2EN Input Synchronous Serial Protocol Serial Clock Enable 2 – SSPSCLK2EN isan asynchronous external enable for SSPSCLK2. SSPSCLK2EN ismultiplexed with the SSPEXTCLK2 alternate function.SSPSCLK3 Inout Synchronous Serial Protocol Serial Clock 3 – SSPSCLK3 is the serial bitclock used to control the timing of a transfer. SSPSCLK3 is generatedinternally (master mode) or is supplied externally (slave mode) asindicated by SSCR1_3[SCLKDIR].Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 172April 6, 2009, Released
Table 69:SSP Serial Port I/O Signals (Continued)Name Direction DescriptionSSPSYSCLK3 Output Synchronous Serial Protocol System Clock 3 – SSPSYSCLK3 is one,four, or eight times the SSPSCLK3 value, depending onSSACD_3[SCDX8] and SSACD_3[SCDB].SSPSFRM3 Inout Synchronous Serial Protocol Serial Frame Indicator 3 – SSPSFRM3, theserial frame indicator, determines the beginning and the end of aserialized data word. SSPSFRM3 is generated internally (master mode)or is supplied externally (slave mode) as indicated bySSCR1_3[SFRMDIR].SSPTXD3 Output Synchronous Serial Protocol Transmit Data 3 – SSPTXD3 is the transmitdata (serial data out) serialized data line.SSPRXD3 Input Synchronous Serial Protocol Receive Data 3 – SSPRXD3 is the receivedata (serial data in) serialized data line.SSPSCLK4 Inout Synchronous Serial Protocol Serial Clock 4 – SSPSCLK4 is the serial bitclock used to control the timing of a transfer. SSPSCLK4 is generatedinternally (master mode) or is supplied externally (slave mode) asindicated by SSCR1_4[SCLKDIR].SSPSYSCLK4 Output Synchronous Serial Protocol System Clock 4 – SSPSYSCLK4 is one,four, or eight times the SSPSCLK4 value, depending onSSACD_4[SCDX8] and SSACD_4[SCDB].SSPSFRM4 Inout Synchronous Serial Protocol Serial Frame Indicator 4 – SSPSFRM4, theserial frame indicator, determines the beginning and the end of aserialized data word. SSPSFRM4 is generated internally (master mode)or is supplied externally (slave mode) as indicated bySSCR1_4[SFRMDIR].SSPTXD4 Output Synchronous Serial Protocol Transmit Data 4 – SSPTXD4 is the transmitdata (serial data out) serialized data line.SSPRXD4 Input Synchronous Serial Protocol Receive Data 4 – SSPRXD4 is the receivedata (serial data in) serialized data line.CLK_EXT Input External Network Clock – CLK_EXT replaces the internal 13 MHz clock.Use CLK_EXT when SSCR0_x[NCS] is set and SSCR1_x[SCLKDIR] iscleared. CLK_EXT is used by multiple SSPs.21.3 Block DiagramsThis section discusses alternate SSP configuration schemas (topologies) and includes a blockdiagram for each schema.21.3.1 Standard SSP Configuration SchemaThe standard SSP configuration schema is the most common method of configuration and allowsone SSP to interface directly to another SSP on another device.This configuration allows for a number of possible configurations. The SSPSCLK can beprogrammed to be either a master or a slave to the peripheral. Likewise, the SSPSFRM can beprogrammed to be a master or a slave to the peripheral, which allows for one physical connection toresult in one of four configurations with only software changes:Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 173
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PXA3xx Design Guide - Marvell

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