PXA3xx Design Guide - Marvell

8 OS Timer InterfaceThis section describes procedures for interfacing the OS timer controller to the PXA3xx processorfamily.8.1 Overview8.2 SignalsThe operating system timers (OSTs) block provides a set of timer channels that allow software togenerate timed interrupts (or wake-up events). In the PXA3xx processor family, these interrupts aregenerated by two sets of timer channels:One set provides one counter and four match registers that are clocked from a 3.25 MHz clock. Thisblock maintains the four Marvell ® PXA25x processor-compatible timer channels.• The other set (additional to the PXA25x processor) provides eight counters and eight matchregisters that are clocked from any of the following:• 32.768 kHz timer clock• 13 MHz clock• An externally supplied clock (CLK_EXT pin) that provides for a wide range of timerresolutions.All references to registers are documented in the Marvell ® PXA30x, PXA31x, and PXA32xProcessor Electrical, Mechanical, and Thermal Specification and Marvell ® PXA30x, PXA31x, andPXA32x Processors Vol. I: System and Timer Configuration Developers Manual, “Section 14:Operating System Timers” unless otherwise noted.See Table 15 for the list of signals used to interface to the OSTs.Table 15:Operating System Timers Interface Signals SummaryName Type Polarity DescriptionEXT_SYNC Input Active High External synchronization signals used to reset timers.CHOUT Output N/A CHOUT is a periodic output clock generated from channel 11.CHOUT is a periodic output clock generated from channel 10.These active-high output signals are used to generate output clocksfrom timer channels 11 and 10, respectively, if these channels havebeen programmed to be periodic.The signal for an active channel that has been programmed to beperiodic will change state each time a match occurs. The signal will below for any non-periodic channel.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 53