PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 86:Bring-up Overview Checklist (Continued)ItemsIf a silicon bug exists that affects a product, document the problem and its implications. Provide:• Logic analyzer or oscilloscope traces• Source code• Methods for easy replication of the problem to the Marvell support teamNOTE:1. probing a crystal’s pin with an oscilloscope may cause it to change its frequency or stop runningMost of the PXA3xx processor family signals are multiplexed so the signals can be configured forone of seven available alternate functions using the GPIO alternate-function select registers. Somesignals can be configured to appear on one of several different pins.For pins that have more than one alternate function, use the check list in Table 87 only for the signalname whose function is configured for a pin with alternate functions.Table 87:Signals to Monitor During Bring-up of the PXA3xx Processor Family Signal Name Pin Connection DetailsPWR_EN PMIC input signal Power Enable (Output) – Should be used to enable thesesupplies:• VCC_APPS• VCC_SRAMSYS_EN PMIC input signal System Enable (Output) – Should be used to enable thesesupplies:• VCC_MVT• VCC_BG• VCC_OSC13M• VCC_PLL• VCC_MEM• VCC_IO1• VCC_IO3• VCC_IO4 (PXA32x only)• VCC_IO6 (PXA32x only)• VCC_USB (PXA30x and PXA32x only)• VCC_MSL• VCC_DF• VCC_LCD• VCC_CARD1• VCC_CARD2• VCC_CI• VCC_BIAS (PXA31x only)• VCC_ULPI (PXA31x only)PWR_OUT 0.1 µF cap to GND Power Out (Power Input Signal)PWR_CAPPWR_CAPPWR_CAPPWR_CAPnBATT_FAULT0.1 µF cap between thepins0.1 µF cap between thepinsPXA3xx processorfamily inputThe PWR_CAP signals connect to external capacitors used toachieve very low power in sleep and deep sleep mode.The PWR_CAP signals connect to external capacitors used toachieve very low power in sleep and deep sleep mode.The nBATT_FAULT signal is an active-low input that signals thePXA3xx processor family that the main battery is low or has beenremoved from the system.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 210April 6, 2009, Released
Table 87:Signals to Monitor During Bring-up of the PXA3xx Processor Family (Continued) Signal Name Pin Connection DetailsClock SignalsPXTAL_IN13.000 MHz crystal orto an external clocksourceProcessor crystal inputPXTAL_OUT 13.000 MHz crystal Processor crystal outputTXTAL_IN32.768 kHz crystal orexternal clock sourceDistributes to the timekeeping control systemTXTAL_OUT 32.768 kHz crystal Distributes to the timekeeping control systemReset SignalsnRESETMust be debounced tocause clean assertionof nRESET for aminimum of 20 msec.ResetActive low, level sensitive input that starts the PXA3xx processorfamily from the reset vector at address 0. Assertion causes thecurrent instruction to terminate abnormally and a reset occurs.When nRESET is driven high, the processor starts execution fromaddress 0. nRESET must remain low until the power supply isstable and the internal 13.000 MHz oscillator has stabilized.nRESET_OUT Output Reset OutAsserted when nRESET is asserted and de-asserts afternRESET is deasserted, but before the first instruction fetch.nRESET_OUT is also asserted for “soft” reset events: sleep,watchdog reset, or GPIO reset.JTAG and Test SignalsnTRSTTDITMSTCKTESTMust be driven beforeor at the same time asthe hardware nRESETpin for correct TAPcontroller and deviceoperation.Not Connected whenJTAG interface is notusedNot Connected whenJTAG interface is notusedTied Low when JTAGinterface is not usedTied Low for normaloperationJTAG test reset. IEEE 1194.1 test reset.JTAG test data input (TDI) The JTAG controller sends data to thePXA3xx processor family using the test signal. The pin has aninternal pull-up resistor, eliminating the need for a connection ifthe JTAG interface is not used.JTAG test mode select (TMS) Selects the test mode required fromthe JTAG controller. The test signal has an internal pull-upresistor, eliminating the need for a connection if the JTAGinterface is not used.JTAG test clockClock for all transfers over the JTAG test interface.Test ModeReserved for manufacturing test. Must be grounded for normaloperation.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 211
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PXA3xx Design Guide - Marvell

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