PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign Guide11.5.5 NAND Flash OperationNAND memories must be attached to the PXA3xx processor family DFI bus. The NAND FlashController (NFC) controls accesses to NAND memories. See and Marvell ® PXA30x, PXA31x, andPXA32x Processors Vol. II: Memory Controller Configuration Developers Manual, “Section 3: NANDFlash Controller” for detailed information on the signals and registers used to operate NANDmemories.11.5.5.1 NAND Block DiagramSee Figure 38 and Figure 39 for illustration of the connection between NAND memory and thePXA3xx processor family memory controller.NotePXA3xx processor family members using the MCP package must have VCC_DFconnected to 1.8 V. NAND devices connected to the MCP versions are 1.8V.NoteThe DF_INT_RNB pin must be connected to the READY/BUSY# pin on NAND deviceconnected to DF_nCS0.Figure 38: Block Diagram Connecting 16 bit NAND to Data Flash InterfaceData Flash Interface(DFI)DF_IODF_INT_RNBDF_ALE_WEx, DF_CLE_nOEDF_nWE, DF_nREGPIOd NoteDF_nCS0 or DF_nCS1IOR/BALE, CLEWE#, RE#WP#CE#x16 NANDNote: GPIOd is any unused GPIO pin. It is used to drive the WP#(Write Protect) pin on the NAND device. GPIO signals must beconfigured within the GPIO controller and are not part of the DFI busas shown. This signal needs an external 10K ohm pull-up resistor.NoteFor NAND booting, use the nCS0 chip select.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 92April 6, 2009, Released
Figure 39: Block Diagram Connecting 8-Bit NAND to Data Flash InterfaceData Flash Interface(DFI)DF_IODF_INT_RNBDF_ALE_WEx, DF_CLE_nOEDF_nWE, DF_nREGPIOd NoteDF_nCS0 or DF_nCS1IOR/BALE, CLEWE#, RE#WP#CE#x8 NANDNote: GPIOd is any unused GPIO pin. It is used to drive the WP#(Write Protect) pin on the NAND device. GPIO signals must beconfigured within the GPIO controller and are not part of the DFI busas shown. This signal needs an external 10K ohm pull-up resistor.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 93
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TablesTable 1: How Design Guide Cha
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PXA3xx Design Guide - Marvell

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