PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 23: Signal: Command (including Address) and ControlTable 25:Command and Control Signals Routing Recommendations for x32 - 2 (x16) DevicesTraceMaxLengthTrace WidthSpacing between this Signal traceand any other Signal traceLayerTL1 (Breakout) 0.4” 3 mils 3 mils HDITL2A and TL2B 0.9” 4 mils 4 mils Buried Micro StripTL3A and TL3B 0.4” 3 mils 3 mils HDI• Recommended maximum via count, including breakout via = 12• Total length of (TL1+TL2A+TL3A) Max = 1.7"• Refer to matching rules for length matching requirement between CMD and SDCLK.10.4.3.3 Length Matching between SDCLK and CMD for x32 - 2 (x16) DevicesTotal length of CMD/Control = Total Length of SDCLK +/- 0.12"10.4.4 Routing Recommendation for 4 - x16 Devices (PXA32xOnly)Figure 24: Signal: DQS, DQ, DQM
DDR Memory Interface (EMPI Bus)EMPI Layout NotesTable 26:MD, DQS, DQM and nSDCS Signals Routing Recommendationsfor 4 - x16 devicesSignalGroupTrace Max Length Trace Width(Min)Spacingfrom anyother signal(Min)LayerMDDQMnSDCSTL1 0.2" 3 mills 3 mills HDITL2A and TL2B 0.6" 4 mills 5 mills BMSTL3A and TL3B 0.1" 3 mills 3 mills HDITL1 0.2" 3 mills 4 mills HDIDQSTL2A and TL2B 0.6" 4 mills 7 mills BMSTL3A and TL3B 0.1" 3 mills 4 mills HDIFigure 25: MA, SDMA10, nSDRAS, nSDCAS, nSDWE, SDCKECopyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 75
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Copyright © 2009 MarvellDoc. No. M
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Figure 42: SPI Protocol Interface B
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TablesTable 1: How Design Guide Cha
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PXA3xx Design Guide - Marvell

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