PXA3xx Design Guide - Marvell

11 Data Flash Interface (DFI)This section describes guidelines for connecting the PXA3xx processor family Data Flash Interface(DFI) to external memory. All DFI memory device types are discussed in this section, which includesdesign considerations for DFI devices covered in the following sections of the Marvell ® PXA30x,PXA31x, and PXA32x Processors Vol. II: Memory Controller Configuration Developers Manual.• Section 2 - Static Memory Controller (SMC)• Section 3 - NAND Flash Controller (NFC)11.1 OverviewThe DFI bus for the PXA3xx processor family supports the following:• NAND Flash• NOR Flash (both Synchronous and Asynchronous AA/D muxed)• SRAM, including variable latency I/O (VLIO) devices• PC Card (PCMCIA) / Compact Flash (PXA32x only)• Non-AA/D muxed devices are supported with the use of external latches to latch the addresssignalsRefer to Marvell ® PXA30x, PXA31x, and PXA32x Processors Vol. II: Memory ControllerConfiguration Developers Manual, “Section 2: Static Memory Controller” for the physical addressesused to configure and map the external memory.11.2 DFI SignalsSee Table 35 for the complete list of DFI-specific signals from the PXA3xx processor family DFIcontroller. Table 35 details how various memory configurations (SRAM, VLIO, PC-Card, 8/16 NAND,16-bit NOR) connect to the DFI signals.Table 35:PXA3xx Processor Family DFI SignalsSignal Name Direction Polarity DescriptionArbitrated SMC and NFC SignalsDF_IO Bidirectional N/A Data/Address bus. Carries data and multiplexed addressinformation for NAND and Static Memory Controller accesses. Theformat of the data and address depends on the bus configurationand whether the access is to a flash or a static memory device.DF_ALE_nWE1DF_ALE_nWE2(PXA32x Only)Output Active Low NAND Flash Controller: Address Latch Enable signal (DF_ALE).Static Memory Controller: Write Enable signal (DF_nWE).NOTE: PXA32x has two signals, DF_ALE_nWE1 andDF_ALE_nWE2, which have the same DF_ALE andDF_nWE functionality.DF_CLE_nOE Output Active Low NAND Flash Controller: Command Latch Enable signal (DF_CLE).Static Memory Controller: Output Enable signal (DF_nOE).Non-Arbitrated Static Memory Controller SignalsCopyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 81