PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideController Configuration Developers Manual, “Section 2: Static Memory Controller” for detailedinformation on the use of DF_ADDR.This example shows the address split between two latches, starting with address A. However,this split point is programmable and is controlled by the CSADRCFGx registers. If the address splitpoint is not configured to be A, then the address lines from the SRAM must be connected to theappropriate latch. Refer to the Marvell ® PXA30x, PXA31x, and PXA32x Processors Vol. II: MemoryController Configuration Developers Manual, “Section 2: Static Memory Controller” for detailedinformation.Figure 34: Block Diagram Connecting SRAM to nCS2 or nCS3nXCVRENDF_IOXCVR *DQData Flash Interface (DFI)LatchnLUAnLLADF_ADDRnCS2 or nCS3DF_CLE_nOE, DF_ALE_WExnBE0nBE1LatchRDnWR *AAAnCSnOE, nWEnLBnUBx16 SRAM* Transceiver is optional for NOR Flash, SRAM,VLIO, and PC-Card depending on bus loading.11.5.3 Variable Latency Input/Output (VLIO) OperationWhen a companion chip is used as a variable-latency I/O device, its functionality is similar to that ofan SRAM. The chip can insert a variable number of wait states through the use of the RDY pin.VLIO devices must be attached to the PXA3xx processor family DFI bus. The static memorycontroller (SMC) control accesses to VLIO devices. Latches are required for non-AA/D muxeddevices to demultiplex the address/address/data bus. Refer to the Marvell ® PXA30x, PXA31x, andPXA32x Processor Electrical, Mechanical, and Thermal Specification for detailed information on thesignal timing for VLIO accesses.VLIO Interfaced to the Data Flash Interface (DFI)See Figure 35 for an illustration of the signals and connections when connecting a VLIO companionchip to the PXA3xx processor family DFI bus. If the VLIO device does not support AA/D muxedoperation (it has separate data and address pins), external latches are needed to latch theaddresses for the VLIO device.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 88April 6, 2009, Released
NoteThe RDY signal is only used when performing VLIO accesses.Figure 35: VLIO Interface Block Diagram - AA/D Muxed Mode on DFI with External LatchesnXCVRENDF_IOXCVR *DQData Flash Interface (DFI)nLUAnLLADF_ADDRnBEREADYnCS2 or nCS3LatchLatchRDnWR *AAAMASKRDYCSx16 VLIODeviceDF_CLE_nOE, DF_ALE_WExOE, WE* Transceiver is optional for NOR Flash, SRAM,VLIO, and PC-Card depending on bus loading.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 89
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PXA3xx Design Guide - Marvell

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