PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideNoteAll low-voltage power supplies must be removed before removing any high-voltagepower supply. If the low-voltage power supplies (VCC_APPS and VCC_SRAM) are notdisabled prior to SYS_EN being de-asserted, VCC_APPS and VCC_SRAM must bedisabled if any of the high voltage supplies are disabled by the de-assertion ofSYS_EN.4.2.2.3 Hardware Reset (nRESET)The nRESET signal is an active-low input which causes the PXA3xx processor family to enter thereset state. Assertion of nRESET cannot be gated and causes the PXA3xx processor family to entera complete and unconditional reset state. The PXA3xx processor family does not recognize anyexternal events while nRESET signal is asserted. nRESET typically is driven directly by an externalPMIC.nRESET is a hard reset that can cause the system to lose state or data when asserted. It is assertedfor a cold start power-on event, or if for any reason a user pushes the system-reset button. ThePMIC must assert nRESET for both events.NoteBecause the power supplies are not on at the power-on reset, nRESET is unknownuntil the power supply driving nRESET is enabled. When the supply powering the circuitdriving nRESET is enabled, nRESET must be asserted and then de-asserted.The minimum assertion time for nRESET is described in the Marvell ® PXA30x, PXA31x, andPXA32x Processor Electrical, Mechanical, and Thermal Specification.While nRESET is asserted, the only activity inside the PXA3xx processor family is the stabilization ofthe timekeeper oscillator and application of the internal reset signals. All remaining internal clocksare stopped and the PXA3xx processor family is fully static. Additionally, all output signals assumetheir reset conditions, and the nBATT_FAULT signal from the PMIC is ignored. The nRESET_OUTsignal from the PXA3xx processor family is asserted when nRESET is asserted.4.2.2.4 Internal Reset (nRESET_OUT)The nRESET_OUT signal is an active-low output that indicates to the PMIC and system thatPXA3xx processor family is in the reset state. nRESET_OUT is asserted by the PXA3xx processorfamily during power-and reset sequences. If PCFR[SL_ROD] is cleared, nRESET_OUT is alsoasserted during S2/D3/C4 mode and S3/D4/C4 mode. If PCFR[GP_ROD] is cleared, nRESET_OUTis also asserted during GPIO reset.4.2.2.5 GPIO Reset (nRESET_GPIO)The nRESET_GPIO signal is an active-low input that is a wake-up event to the PXA3xx processorfamily and can be used to generate a GPIO reset. GPIO reset is used as a “soft” reset that allows auser to reset the PXA3xx processor family while maintaining data in external memory devices andthe real-time clock. GPIO reset is invoked when nRESET_GPIO is asserted (or whenPMCR[SWGR] is set). nRESET_GPIO contains an internal resistive pull-up that is enabled duringpower-on, hardware, watchdog, and GPIO resets. This pull-up is disabled when PCFR[PUDH] iscleared.In many handheld systems, nRESET_GPIO is asserted when a user presses the reset button on theback of the device.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 40 April 6, 2009, Released
4.2.2.6 EXT_WAKEUPThe EXT_WAKEUP signals are used (PXA30x and PXA31x use only EXT_WAKEUP) as aS2/D3/C4 mode or S3/D4/C4 mode wake-up source and function as a S3/D4/C4 mode wake-upeven if S3/D4/C4 mode is entered due to the assertion of nBATT_FAULT. If nBATT_FAULT causedentry into S3/D4/C4 mode, then this pin is the only possible wake-up source. Therefore, if usingnBATT_FAULT to indicate power supply health, this pin must be provided as a dedicated input.The EXT_WAKEUP signals are on the VCC_BBATT domain and thus this input has its Vil andVih levels based upon VCC_BBATT voltage. See the Marvell ® PXA30x, PXA31x, and PXA32xProcessor Electrical, Mechanical, and Thermal Specification for details.The EXT_WAKEUP signal contains an internal resistive pull-down, and the EXT_WAKEUPsignal contains an internal resistive pull-up. The pull-down and pull-up are enabled during power-on,hardware, global watchdog, and GPIO resets, and disabled when PCFR[PUDH] is cleared. Inaddition, EXT_WAKEUP can be used as general-purpose I/O pins and are controlled in“Power Manager EXT_WAKEUP[1:0] Control Register (PECR)” register. See Marvell ® PXA30x,PXA31x, and PXA32x Processors Vol. I: System and Timer Configuration Developers Manual ,“Section 8: Services Power Management” for more information on this register.The PXA3xx processor family also detects additional wake-up inputs that cause exit from S2/D3/C4mode. Refer to Marvell ® PXA30x, PXA31x, and PXA32x Processors Vol. I: System and TimerConfiguration Developers Manual , “Section 8: Services Power Management” for more informationon these wake-up sources.NotePXA30x Processor and PXA31x Processor only use EXT_WAKEUP.NoteThe EXT_WAKEUP signal is not detected as a wake-up-from-S2/D3/C4 modeuntil after S2/D3/C4 mode has been entered. S2/D3/C4 mode entry is complete whenPWR_EN has been deasserted. Similarly, the EXT_WAKEUP signal is notdetected as a wake-up-from-S3/D4/C4 mode until after S3/D4/C4 mode has beenentered. S3/D4/C4 mode entry is complete when SYS_EN is de-asserted.4.2.2.7 Power Manager I 2 C Clock (PWR_SCL)The PWR_SCL signal is the power-manager I 2 C clock to the external PMIC. The I 2 C serial busoperates up to 400kbits/sec.NoteThe PWR_SCL signal contains an internal resistive pull-up that is enabled duringpower-on, hardware, global watchdog, and GPIO resets and is disabled whenPCFR[PUDH] is cleared. Refer to Marvell ® PXA30x, PXA31x, and PXA32x ProcessorsVol. I: System and Timer Configuration Developers Manual , “Section 8: ServicesPower Management” for more information.4.2.2.8 Power Manager I 2 C Data (PWR_SDA)The PWR_SDA signal is the power-manager I 2 C data signal to the external PMIC. PWR_SDAfunctions like an open-drain signal, so either the power-manager I2C controller or the PMIC can pulldown PWR_SDA to a logic-low level.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 41
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PXA3xx Design Guide - Marvell

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