PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 72: USB Host (Port 2) Differential Connections Block DiagramPXA3xxProcessorUSB HostController - Port 2USBHPEN2CONTROL+5VVBUS1USB HostCableConnectorVBUS (+5V)USBHPWR*USB PowerSwitch Circuitry(Required)FAULT4GNDUSBOTG_PUSBOTG_NC PR SR SR PTermination,Filtering, andESD ProtectionCircuitry(Optional)32USB D+USB D-*Note: USBHPWR can be used to detect faults for allthree host ports (Port 1, 2, 3)C PR PC P= 68 - 75 pFR S= 10 - 25 OhmsR P= 15 KOhms20.3.3 USB Host Single-Ended Connections (Port 3)Host controller Port 3 is used only with single-ended connections as shown in Figure 73.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 168April 6, 2009, Released
Figure 73: PXA3xx Processor Family Host 3 Connections to External USB TransceiverUSB HostController123Transmit enableUSB_P3_4VMOVPOSPEEDD-D+USB_P3_6OE_nMust pullHigh or Low*RCVVPUSB_P3_2USB_P3_1VMPXA3xx ProcessorUSB_P3_5USB_P3_3External USBTransceiverNoteThe “SPEED” signal does not exist for PXA3xx processor family host Port 3. The“SPEED” signal of the external device must be tied high or low. Program PXA3xxprocessor family host 3 to match the external device speed.20.4 Layout NotesThe USB power supply must be +5.0 V (per the USB specification). However, the PXA3xx processorfamily does not have 5.0 V-tolerant inputs. Provide an external device to interface the USBHPENxand USBHPWR pins to the power supply and over current detection circuits.NoteThere is no USBHPWR2 input signal/function on the PXA3xx processor family. Use anexternal circuit to OR the overcurrent for port 2 back into USBPWR1The C P and R S components are required by the USB host controller for USBH1_P, USBOTG_P,USBH1_N, and USBOTG_N signal compliance with the USB specification and must be placed asclose as possible to the Monahans USBH1_P, USBOTG_P, USBH1_N, and USBOTG_N balls.The R P pulldown resistors shown on the USBH1_P, USBOTG_P, USBH1_N, and USBOTG_Nsignals are required per USB specification.Terminations and filtering for signal integrity and electrostatic discharge (ESD) protection circuitryare recommended, but varies for different systems depending upon layout and end applicationenvironment.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 169
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Copyright © 2009 MarvellDoc. No. M
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Figure 42: SPI Protocol Interface B
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TablesTable 1: How Design Guide Cha
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PXA3xx Processor FamilyDesign Guide
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