PXA3xx Design Guide - Marvell

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Table 79: Bluetooth UART Interface Signals ..................................................................................................190Table 80: CIR Signal Description....................................................................................................................191Table 81: PWM Interface Signal List ..............................................................................................................193Table 82: USIM Interface Signals ...................................................................................................................196Table 83: USIM Card Signals .........................................................................................................................197Table 84: I2C Signal Description ....................................................................................................................201Table 85: PXA3xx Processor Family Schematic Checklist.............................................................................203Table 86: Bring-up Overview Checklist...........................................................................................................209Table 87: Signals to Monitor During Bring-up of the PXA3xx Processor Family ............................................210Table 88: Layout Checklist .............................................................................................................................212Table 89: Low Power Considerations Checklist .............................................................................................213Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 17
Page 5 and 6: 10.2 Signals ......................
Page 7 and 8: 17.2 Signals ......................
Page 9 and 10: 26.2 Signals ......................
Page 11 and 12: Copyright © 2009 MarvellDoc. No. M
Page 13 and 14: Figure 42: SPI Protocol Interface B
Page 15: TablesTable 1: How Design Guide Cha
Page 19 and 20: 1 IntroductionThis manual outlines
Page 21 and 22: 2 PCB Design GuidelinesThis section
Page 23 and 24: Figure 2:Recommended Layer Assignme
Page 25 and 26: Table 4:PCB Dimensions for Copper-D
Page 27 and 28: Table 5:Decoupling Capacitors Per V
Page 29 and 30: Table 7:VCC_DF Decoupling Recommend
Page 31 and 32: 3 Minimizing Power Consumption3.1 O
Page 33 and 34: • Configure OSCC[TENS0] appropria
Page 35 and 36: 4 Clocks and Power Interface4.1 Ove
Page 37 and 38: The PXA3xx processor family has 20
Page 39 and 40: Table 11:VoltageSupplyVCC_USBPower
Page 41 and 42: 4.2.2.6 EXT_WAKEUPThe EXT_WAKEUP si
Page 43 and 44: 4.4 Modes of OperationsThis section
Page 45 and 46: Figure 6:PXTAL_IN and PXTAL_OUT Con
Page 47 and 48: 5 One-Wire Interface5.1 Overview5.2
Page 49 and 50: 6 Interrupt Controller InterfaceThi
Page 51 and 52: 7 Real-Time Clock Interface7.1 Over
Page 53 and 54: 8 OS Timer InterfaceThis section de
Page 55 and 56: • The frame-detect signal from SS
Page 57 and 58: 9 JTAG DebugThis section describes
Page 59 and 60: 9.5 JTAG Board ConnectionFigure 11
Page 61 and 62: 9.7 OperationFor information on usi
Page 63 and 64: DDR Memory Interface (EMPI Bus)Over
Page 65 and 66: DDR Memory Interface (EMPI Bus)Bloc
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DDR Memory Interface (EMPI Bus)EMPI
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Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
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11 Data Flash Interface (DFI)This s
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Table 35:PXA3xx Processor Family DF
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Figure 32: PXA32x DFI Memory Config
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appropriate latch. Refer to Marvell
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NoteThe RDY signal is only used whe
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To prevent erroneous nPCE assertion
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Figure 39: Block Diagram Connecting
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12 MultiMediaCard/SD/SDIO Card Cont
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Table 36:Multimedia Card/SD/SDIO Ca
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on the VCC_CARD2 power domain or th
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Table 41:Consideration of Power Dom
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shown in Figure 41 supports the use
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12.3.6 SPI Protocol Layout NotesThe
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13 LCD Interface13.1 SignalsThe PXA
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Table 45:Passive Display Pins Requi
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etween the PXA3xx device and the pa
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Figure 45: Active Color 18-bits-per
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Figure 47: Active Color 16bpp to 24
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Accordingly, the pin interface betw
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• Maximum frequency of operation
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Figure 52: Signals: LDD[17:0], L_PC
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14 Mini-LCD ControllerThis section
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15 Keypad InterfaceThis section des
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Figure 53: Keypad Interface Diagram
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KP_MKOUT. The number of columns in
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15.5.2 Keypad Matrix and Direct Key
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16 Quick Capture InterfaceThis sect
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17 USB 1.1 Full Speed OTG and Devic
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Table 54:USB Device Controller Inte
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Figure 57: USB Device Controller In
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Figure 58: Self-Powered Device when
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3. Enter S2/D3/C4 mode.When a USB c
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Table 56:Host Port 2 OTG Transceive
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Figure 63: Connection to External O
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See Table 57 and Table 58 for defin
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18 USB High-Speed Device Controller
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Figure 66: USB 2.0 Device Controlle
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T3- Microstrip construction, 50 Ω
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19 USB High-Speed Controller (U2D)
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Table 61:ULPI 3/6-pin Serial Mode S
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Figure 69: Recommended Layer Stack
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20 USB 1.1 Host InterfaceThis secti
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Table 67:USB Host Controller Interf
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Figure 71: PXA3xx Processor Family
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Figure 73: PXA3xx Processor Family
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21 SSP Port Interface21.1 Overview2
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Table 69:SSP Serial Port I/O Signal
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Figure 75: External Clock Source Co
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Figure 77: Internal Clock Enable Co
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22 AC ’97 InterfaceThis section d
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Configuration Developers Manual,
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22.6 Routing Recommendations22.6.1
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22.6.3 Topology # 3: SDATA_IN with
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23 UART InterfacesThis section desc
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Table 78:Full Function UART Interfa
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24 Consumer Infrared InterfaceThis
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25 Pulse-Width Modulator Interface2
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26 USIM Controller InterfaceThis se
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26.2.2 USIM Card Interface SignalsS
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Figure 89: Interfacing the Second U
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27 Inter-Integrated Circuit (I 2 C)
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ADesign ChecklistThis Appendix is a
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Table 85:PXA3xx Processor Family Sc
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Table 85:PXA3xx Processor Family Sc
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A.2 Bring-up ChecklistTable 86:This
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Table 87:Signals to Monitor During
Page 213 and 214:
Table 88:ItemsLayout Checklist (Con
Page 215:
Back CoverMarvell Semiconductor, In
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PXA3xx Design Guide - Marvell

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