PXA3xx Design Guide - Marvell

PXA3xx Processor FamilyDesign Guide• Master to SSPSCLK / master to SSPSFRM• Master to SSPSCLK / slave to SSPSFRM• Slave to SSPSCLK / master to SSPSFRM• Slave to SSPSCLK and slave to SSPSFRMSee Figure 74 for illustration of the physical connections of the above configurations.Figure 74: Standard SSP Configuration Schema Block DiagramSSPSCLKPXA3xxProcessorIntel ® Monahans ProcessorSSPSFRMSSPRXDSSPTXDSSPCLKEN/SSPEXTCLKPeripheral SSPSSP_000_P221.3.2 External Clock Source Configuration SchemaThe external clock source configuration allows for an external clock source to be the SSPCLKgeneration source. Using an external clock source is different than the SSPSCLK operating as aslave. When using an external clock source, the SSPSCLK is still a master; however, the externalclock replaces the internal 13 MHz clock for PXA30x processor or 26 MHz internal clock for PXA31xprocessor (with SSCR0_x[52MM] set to one) as the source clock for SSPSCLK generation.The external clock source configuration allows SSPSCLK frequencies with bases other than13 MHz, or for using a network clock to serve as a clock source for an SSP, but the SSP is still themaster of SSPSCLK.See Figure 75 for illustration of the physical connection of the external clock source configuration.Doc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 174April 6, 2009, Released