PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideNoteWhen designing shared 1.8 V power domains, Marvell recommends that customerscontact their PMIC vendors to help design and characterize optimal noise filteringcircuits.2.4 Silicon Daisy Chain (SDC) Evaluation UnitsMarvell offers SDC evaluation units that have been internally shorted together (to the silicon) in adaisy-chain pattern. This pattern ensures that the I/O path of the package is complete through theball, substrate, lead beam or bond wire, silicon, and back down through a separate I/O path. Theseunits are useful for setup and evaluation of manufacturing equipment.2.5 RoHS (Lead Free Compliance)NoteAll production Marvell ® PXA30x, PXA31x, and PXA32x Processor parts are RoHS leadfreeDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 30April 6, 2009, Released
3 Minimizing Power Consumption3.1 OverviewThe PXA3xx processor family uses a complex power-management system that provides the bestpossible power use. Marvell recommends taking additional steps to minimize total powerconsumption. This section describes recommended methods for measuring power and providesdetailed recommendations for minimizing overall power usage.3.2 Achieve Minimum Power Usage During All PowerModesThe following are methods for achieving the lowest power consumption during all power modes:• Connecting the crystal signals to an external oscillator achieves the lowest power consumptionby the PXA3xx processor family. Yet, the power consumed by the oscillator is considered fortotal system power use. Use caution when selecting an external oscillator rather than anexternal crystal. Verify the external oscillator is equally or more efficient than the PXA3xxprocessor family using a crystal.• Design the system so that all power domains use the lower voltage level supported within thespecifications. Specifically, VCC_DF and other I/O VCC rails are at 1.8 V whenever possible.• Ensure I/O voltage levels track power domain levels; that is, for VCC_MEM = 1.8 V, all MD pinsmust be driven at 1.8 V; otherwise negative current could occur.• Ideally, the system design allows measurements of power across all domains individually,helping designers isolate high current problems down to a specific voltage domain.• Enable all internal pull-up/pull-down resistors on GPIOs, reserved, and unused chip select pins,which is accomplished through the MFPR register settings:• In addition to the assigned multi-function options, each multi-function pin has an assignedregister (MFPR) that allows the enabling of pull-up or pull-down functions. For example, toset PULLDOWN_EN on GPIO0, first set MFPR[PULL_SEL] (bit 15) at physical address0x40E1_0124, then set MFPR[PULLDOWN_EN] (bit 13) at physical address0x40E1_0124. See Marvell ® PXA30x, PXA31x, and PXA32x Processors Vol. I: System andTimer Configuration Developers Manual, “Section 4: “Pin Descriptions and Control”.• Review all clock and memory controller settings. Default settings used in S0/D0/C0 andS0/D0/C1 might not achieve optimal power usage for low power modes.3.3 Achieve Minimum Power Usage During S3/D4/C4Methods for achieving lowest power consumption during S3/D4/C4 power mode:• Ground VCC_APPS and VCC_SRAM to attain the lowest power consumption and validate thedesign.• To verify that the PXA3xx processor family PMU is in the S3 state use JTAG to verify thatPSR[SS3S] = 0b1. This step is optional.• Clear PCFR[PUDH]. This disables the pull-up and pull-down registers for nGPIO_RESET,EXT_WAKEUP, PWR_SCL and PWR_SDA.• Configure OSCC[TENS3] appropriately. This setting is system dependent.• Refer to the Marvell ® PXA30x, PXA31x, and PXA32x Processor Electrical, Mechanical, andThermal Specification for the proper configuration state for the pins during S3/D4/C4.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 31
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PXA3xx Design Guide - Marvell

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