PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideFigure 64: Connection to OTG IDUSB DeviceControllerUP2OCR[IDEN]GPIO[41]ENBOTG ID100 K OhmOTG ID10 OhmPXA30x Processor17.4.7 Interface to External USB Transceiver (non-OTG)In addition to the OTG interfaces to external transceiver and charge pump devices, the UDC andUSB host controller interfaces to a non-OTG external USB transceiver through the single-endedinterface with the GPIOs. In this mode, the GPIOs provide unidirectional connections to an externaltransceiver and the external transceiver provides bidirectional connections for D+ and D- to theUSB. This mode is selected when single-ended zero (SEO) in the “USB Port 2 Output ControlRegister (UP2OCR)” is set to 2 or 3. See Figure 65 for illustration of the PXA30x processor orPXA32x processor connection to an external USB transceiver.Figure 65: PXA30x and PXA32x Processor Connection to External USB TransceiverUSB HostController123Transmit enableUSB_P2_4VMOVPOSPEEDD -D +USB DeviceControllerD +/D -UP2OCR[EXSP]USB_P2_6USB_P2_7OE_nRCVVPTransmit enableUSB_P2_2UP2OCR[SE0S]USB_P2_1VMPXA300 ProcessorUSB_P2_5USB_P2_3External USBTransceiverDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 148April 6, 2009, Released
See Table 57 and Table 58 for definitions associated with the possible combinations of data whileusing the external USB transceiver mode.Table 57:Output to External USB TransceiverP2_6/P3_6 P2_4/P3_4 Result0 0 SE00 1 Logic “0”1 0 Logic “1”1 1 “SE1” (not allowed)Table 58:Input from External USB TransceiverP2_5/P3_5 P2_3/P3_3 Result0 0 “SE0”0 1 Low Speed1 0 Full Speed1 1 “SE1” (not allowed)Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 149
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Copyright © 2009 MarvellDoc. No. M
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Figure 42: SPI Protocol Interface B
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TablesTable 1: How Design Guide Cha
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PXA3xx Processor FamilyDesign Guide
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PXA3xx Design Guide - Marvell

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