PXA3xx Design Guide - Marvell

• Maximum frequency of operation supported by this design guide (freq. of L_PCLK_WR) is33 MHz.13.3.2 Recommended Layer Stack UpFigure 50: SIx Layer Board Stack Up ExampleLAYER 1 HDI 90 OhmsLAYER 2 BMS 60 OhmsLAYER 3 Power or Ground FloodLAYER 4 Power or Ground FloodLAYER 5 BMS 60 OhmsLAYER 6 HDI 90 Ohms13.3.3 LCD Routing RecommendationsThe Table 48 lists the signals for which these recommendations are provided.Table 48:LCD SignalsSignalsLDD[17:0]L_PCLK_WRL_LCLK_A0L_FCLK_RDLDD[7:0]TypeOutputOutputOutputOutputInput13.3.3.1 Single Load DesignsFigure 51 shows a point -to-point topology for single load cases (no stubs). LDD, L_LCLK_A0,L_FCLK_RD and L_PCLK_WR needs to be matched within +- 1.0 inchCopyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 119