PXA3xx Design Guide - Marvell

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PXA3xx Processor FamilyDesign GuideTable 35:PXA3xx Processor Family DFI Signals (Continued)Signal Name Direction Polarity DescriptionDF_SCLK_E Output N/A Output ClockThis is generated by the combination of the SMCFS bit in theApplication Subsystem Clocks Configuration Register (ACCR) andthe DF_CLKDIV bit in the Clock Configuration Register(MEMCLKCFG).nCS Output Active Low Chip Selects• nCS and nCS (PXA30x and PXA31x Only)• nCS and nCS (Configured on GPIO pins)•PXA32x - GPIO and GPIO•PXA31x and PXA30x - GPIO and GPIOnLUA Output Active Low Latch Upper AddressThis signal can be used to latch the high order address bits of thecycle from the address bus in an external device.nLLA Output Active Low Latch Lower AddressThis signal can be used to latch the low order address bits of thecycle from the address bus in an external device.nXCVREN Output Active Low External Transceiver EnableThis signal can be used to enable an external transceiver for SMCaccesses.NOTE: For PXA30x and PXA31x nXCVREN corresponds toGPIO. For PXA32x nXCVREN corresponds tonXCVREN (Dedicated).DF_ADDR Output Active High Low-order address bitsThis can be used as the lowest four address bits during a bursttransfer instead of the values in the lower address latch, thisallows higher performance data transfer by avoiding most of theLLA cycles.NOTE: These 4 address signals are present no matter whichaddressing mode is used for flash, SRAM and VLIOaccesses. Not used for CF Card accesses (PXA32x Only)nBE Output Active Low Data byte enable.nBE corresponds to DF_IOnBE corresponds to DF_IO0 = Do not mask out corresponding byte1 = Mask out corresponding byteRDY Input Active Low Variable latency VLIO signal for inserting wait states.0 = Busy1 = ReadyNOTE: For PXA30x and PXA31x RDY corresponds to GPIO.For PXA32x RDY corresponds to GPIODREQ Input Active Low DMA Request (PX32x Only)External DMA request pin used by a companion chip. Positiveedge triggered signal that notifies the DMA Controller of a StaticMemory Controller access requests.Non-Arbitrated NAND Flash Controller SignalsDoc. No. MV-S301368-00 Rev. A Copyright © 2009 MarvellPage 82April 6, 2009, Released
Table 35:PXA3xx Processor Family DFI Signals (Continued)Signal Name Direction Polarity DescriptionDF_nCS Output Active Low Chip SelectsNOTE: For devices booting from NAND, nCS must be used.For more information on supported boot configurationsrefer to the PXA3xx Boot ROM Reference Manual.DF_nWE Output Active Low Write EnableDF_nRE Output Active Low Read EnableDF_INT_RnB Input Active Low Ready/Busy#0 = Busy1 = ReadyNOTE: Must be connected to the NAND device on nCS whenbooting from a NAND device.11.3 Block DiagramSee Figure 31 and Figure 32 for an illustration of how the PXA3xx processor family DFI memorycontroller signals are used to interface to NOR Flash, SRAM, VLIO, Compact Flash, and 8/16-bitNAND Flash.Copyright © 2009 MarvellDoc. No. MV-S301368-00 Rev. AApril 6, 2009, Released Page 83
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Copyright © 2009 MarvellDoc. No. M
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Figure 42: SPI Protocol Interface B
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TablesTable 1: How Design Guide Cha
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PXA3xx Design Guide - Marvell

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