8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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BIPOLAR LSI DIVISION 8X330 PACKAGE/PIN DESIGNATIONS VCC VR VCR C2 Cl CCO PUP PDN 8X330 FLOPPY DISK IV7 FORMATTER- DC3 CONTROLLER iVs DC2 DCl DSS DS4 DS3 DSl iVs IV4 IV3 iV2 iV1 IVO WC sc MCLK PIN NO. MNEMONIC & DEFINITION FUNCTION 1,20 2, 3 4 5 6-12 13-1? 18 GND X1, X2 Ground Crystal inputs Data write Data read DC1-DC? Disk commands Circuit ground ME Inputs from a crystal that determines frequency of an on-chip crystal oscillator. A series of negative-going pulses transmitted to the disk drive. The data write signal produces pulses (with precompensation, if required) for data and clock in accordance with the applicable encoding rules (FM, MFM or M2FML Negative-going pulses transmitted from the disk drive to a Schmitttrigger input of the 8X330; these pulses represent encoded data and clock from the disk media. Seven outputs from the 8X330 that allow general-purpose control, of one or more disk drives. DS1-DS5 Disk status Five general-purpose Schmitttrigger inputs from the disk drive (or drives) that provide status information for the 8X300. Power fail Schmitt-trigger input from external logic that is active (low) when the "user-sensed" power supply voltage drops below a predetermined value. PIN NO. MNEMONIC & DEFINITION FUNCTION 19 21 22 23 24 25-31 33 34 35 36-3? 38 39 40 MCLK SC WC Write gate Master enable Master clock When active (low), this 40- milliampere open-collector output enabies writing to the disk media. When PF is low, the write gate is inhibited during periods of power supply uncertainty. When this input signal is active (low), the 8X330 can be accessed and enabled by the 8X300. (Refer to the LB and RB pinout discriptions of the 8X300 for further detail.) When active high and with ME in the active-low state, this input signal provides a means whereby the 1/0 output from the 8X300 is interpreted as an enabling address (provided there is an address match) or as input data (if one of the 8X330 registers has already been selectedL Select command When this signal is active (high), the information output on pins IVO IV? of the 8X300 is interpreted as an address input by the 8X330. Write command When this signal is active (high), the information output on pins IVO IV? of the 8X300 is interpreted as input data by the 8X330. IVO-IV? Input/output Eight three-state input/output lines lines that provide bidirectional data transfers between the 8X300 and the enabled 1/0 device; IV? is the Least Significant Bit. CCO C1, C2 VCR VR Vee Pump down output Pump up output Open-collector output of on-chip phase detector which indicates (by a negative-going, quantized, pulse-width modulated signal) that internal CCO frequency is too high. Open-collector output of on-chip phase detector which indicates (by a negative-going, quantized, pulse-width modulated signal) that internal CCO frequency is too low. Frequency Con- Variable input current from extrol Input for Cur- ternal low-pass filter that rent-Controlled controls the frequency Oscillator of the oscillator. Capacitor input Inputs for capacitor that determinals termines center frequency of the current-controlled oscillator. Regulated supply DC voltage input from emitvoltage ter of external series-pass transistor; this voltage powers internal logic of chip. Reference voltage Supply voltage +5 volt power. Reference voltage output to base of series-pass transistor; this reference controls VCR. 4 Gi!lDotiCG
BIPOLAR LSI DIVISION SYSTEM INTERFACE A typical floppy disk controller using an 8X300 microcontroller and the 8X330 is shown in Figure 2. The non-shaded portion of this particular configuration can service the command, status, and input/output requirements of two double-sided disk drives and, under software supervision, the system can read/write single-density (FM) or doubledensity (MFM/M2FM) codes. Interface requirements are simple-on one hand, consisting of the 8X300 microcontrollE?r and, on the other, the two disk drives. <strong>Al</strong>l 8X330 control and data registers directly linked to the microprocessor interface (Figure 1) are addressable and appear to the 8X300 as simple I/O ports; a 13-bit address bus and a 16- bit instruction bus provide communications between the 8X300 and up to 8K of microprogram storage. The disk-drive interface consists of seven (7) output control lines (OC1-0C7l, five (5) input status lines (OS1-0S5), a write gate (WG), a data- write output (OW), and a data-read input (DR), The twelve command/status lines are not dedicated; thus, the user can assign system functions to best suit a given application. As shown in Figure 2, all control lines except WG are buffered to accommodate a reasonable distance between the controller and the disk media; the Write Gate, being a 40-milliampere output, requires no buffering. As shown by the shaded part of Figure 2, the control and status lines can be expanded with peripheral hardware-the 8T32 (jn this example) being only one method of implementation. Using this particular technique, one I/O port is totally dedicated to output control, whereas, the other port is totally dedicated to input status. With additional hardware and supporting software, the disk-drive system can be expanded without limit; however, from a point of being practical, five or six drives is sufficient for most applications. By using the programmable features of the 8X330, the user can emphasize and prioritize those system parameters that are most important-economics, reliability and/or speed. USER-DEFINED DRIVE-CONTROL SIGNALS TO DISK DRIVES HEAD DIRECTION--t>--::--- HEAD STEP [:>- DISKSELECT#I~ SC wc MCLK LBorRB DISK SELECT #2----:-----t:>- SIDESELECT~ HEAD LOAD [:>- LOW WRITE CURRENT ~ ---[>--; 13 MICROPROGRAM STORAGE FROM DISK DRIVES Figure 2. Typical Interface Using an 8X300 Microcontroller Gi!lDOliCG 5
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
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The second, and most desirable, met
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2.2 8X300 TIMING To understand the
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XI ~~------------------------------
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Table 2-3. 8X300 AC Electrical Char
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2.2.2 Timing Calculations It is an
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INSTRUCTION •••• tI INPUT I
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Xl _Il_n_r Not. 2 RESUME NORMAL OPE
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Normally, the instruction cycle tim
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LB/RB del~ (TIIBS) or the delay tim
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Table 2-4. Bit Manipulation Functio
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The following sections provide gene
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6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142: PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144: PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146: DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148: APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150: 8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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