8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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Preface The Signetics 8X300 Design Guide is intended to supply the design engineer with a concentration of valuable and, in some cases, previously unpublished information relative to the implementation of systems using the Signetics 8X300 Microcontroller and its compatible devices. The material contained within this handbook is arranged in such a manner as to provide the user with the following: 1. An overview of the 8X300 family as a state-of-the-art design tool. 2. Tutorial information relative to the operation and use of the Signetics 8X300 Microcontroller and its compatible devices. Additional information necessary for the design of systems utilizing the Signetics 8X300 Microcontroller may be obtained from the following Signetics documents: • Signetics 8X300 Programming Manual • Signetics Microcontroller Cross Assembly Program Manual • Signetics Data Sheets for specific devices to be used
CONTENTS Chapter Page Preface ........................................... i 1.0 8X300 F AMIL Y AS ST ATE-OF -THE-AR T DESIGN TOOLS ••••••• 1-1 1.1 INTRODUCTION •••••••••••••••••••••••••••••• 1-2 1.2 DESIGN ADV ANT AGES OF THE SIGNETICS 8X300 MICROCONTROLLER •••••••••••••.•••••••••••• 1-4 1.3 DESIGN CONSIDERATIONS •••••••••••••••••••••• 1-5 2.0 THEORY OF OPERATION •••••••••••••••••••••••••••••• 2-1 2.1 CPU ARCHITECTURE •••••••••••••••••••••••••• 2-3 2.1.1 Decode and Control Logic ••••••••••••••••• 2-3 2.1.2 Arithmetic Logic Unit ••••••••••••••••••• 2-4 2.1.3 Program Address Logic ••••••••••••••••••• 2-5 2.1.4 Bus Structure and Control •••••••••••••••• 2-7 2.1.5 Internal Working Storage •••••••••••••••••• 2-9 2.1.6 Bit Manipulation Logic ••••••••••••••..••. 2-10 2.1.7 Oscillator •••••••••••••••••••••• ,•••••. 2-13 2.2 SIGNETICS 8X300 TIMING ••••••••••••••••••••••• 2-16 2.2.1 Instruction Cycle ••••••.•••••••••••••••• 2-16 2.2.2 Timing Calculations ••••••••••••••••••••• 2-22 2.3 THE 8X300 INSTRUCTION SET •••••••••••••••••••• 2-31 2.4 INTERF ACE PRINCIPLES .•••••••••••••••••••••• 2-33 2.4.1 Memory Interface ••••••.•••••••••.••••• 2-34 2.4.2 I/O Interface •••••••••••••••••••••••••• 2-40 2.4.3 Data Conversion ••••••••••••••••••••••• 2-42 ii
Page 1 and 2: 8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3: SIGNETICS ® reserves the right to
Page 7 and 8: LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10: FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12: 1.1 INTRODUCTION The Signetics 8X30
Page 13 and 14: 1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16: In the area of development systems,
Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56:
2.4.2 I/O Interface Typical interfa
Page 57 and 58:
The preceding descriptions should n
Page 59 and 60:
~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62:
stored in the successi ve-approxima
Page 63 and 64:
g) Priority logic - If more than on
Page 65 and 66:
~LK------------------------~ +S~ 1
Page 67 and 68:
2.5.2 Interrupt Control (Handshake)
Page 69 and 70:
The positive edge of the INTERRUPT
Page 71 and 72:
the writing of I/O addresses is inh
Page 73 and 74:
The outputs of the flip-flops are u
Page 75 and 76:
10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78:
BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80:
BIPOLAR LSI DIVISION phase. During
Page 81 and 82:
MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84:
MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86:
BIPOLAR LSI DIVISION AC CHARACTERIS
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111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90:
: ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92:
BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94:
UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96:
BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98:
81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100:
BUS IN I EIEICE lEGIS I EI lIllY PR
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PRELIMINARY elPOLAR LSI DIVISION AC
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BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106:
BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108:
BIPOLAR LSI DIVISION Command/Status
Page 109 and 110:
FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112:
BIPOLAR LSI DIVISION Data Processin
Page 113 and 114:
BIPOLAR LSI DIVISION DC CHARACTERIS
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~ FLOPPY DISK FORMATTER fGONTROLLER
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-- u Current-Controlled Oscillator
Page 119 and 120:
2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124:
PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126:
8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
Page 131 and 132:
1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134:
BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140:
= SABEl =---=========--__ F PRELIMI
Page 141 and 142:
PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150:
8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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