8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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2.1.4 Bus Structure and Control
Figure 2-4. Program Address Logic Data Flow
The 8X300 bus structure, depicted in Figure 2-1, consists of
dedicated Instruction and Instruction Address buses, and a
multiplexed I/O bus. This bus structure allows direct
implementation of a totally independent read only Program Memory
of up to 8192 words by 16-bits. The 13-bit Program Control logic
allows the order of program execution to be altered by instructions,
either unconditionally or under conditions determined from selected
data.
Interface with external working storage (RAM) and user equipment
is through the I/o bus. This bus carries either address information
or data, and is accompanied by two Data-I/O control lines (WC and
SC) which indicate to external circuitry which of the two types of
information is on the bus. Ordinarily the 8-bit I/o bus would only be
capable of addressing a maximum of 156 bytes of memory and/orI/O
registers, but --1brough--1be use of two additional complementary
control lines (LB and RB) this capability has been expanded to a
maximum of 512. This is accomplished by grouping the memory-I/O
into two banks of 256 bytes and/or devices, and using one control
line to select each. It should be noted that only one device per bank
may be enabled at any given time. Timing for the external memory
and I/o is by means of the MCLK signal from the Signetics 8X300.
The five control lines function as follows:
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