8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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In total, eight interupt requests may be given. As an example, INTREQA is chosen as an edge-trigger interrupt while INTREQH is treated in a handshake procedure. The eight interrupt request signals, INTREQA through INTREQH, either trigger an interrupt flip-flop or feed directly into a masking gate, with which it is possible to inhibit one or more chosen levels. G- 0- 7474 INTFPA A- - C INTREO _ 0 _ '5V R rc:.. ............. 1_.1..,-,1 INTERRUPT SIGNAL I }- 7 r--------L...._,~ I I I I I I I I I I I I I - 6 EO GS CLEAR - 5 - 40 40 ........ MCLK - l INTERRUPT ~ CODE - -=- -4 A2 f--- 3D 301---+--1-+-1 A -3 -2 I ... -1 or+~~~~+-D-' O RESET--_-- INT MASK 74148 74175 __ ~~ El +--, 1 -'- ~ - I \ 'T~ I I I _1- INTERRUPT INHIBIT A1 ~ 20 A0t-- 10 CLOCK 201---~+-IB 101----~C G2A 7413B I C 7474 ACKN-H - -H o S 0 f- ~""""",,""'I G2B~ Y7 I I I I I ; 1 G1 YO~~t---- AA T ~ ~ ______---1 ACKNOWLEDGE INTERRUPT ACKNOWLEDGE 1 I 1 I 1 Figure 2-38. Priority Interrupt Level Logic INT MASK signals come from an I/O port, so that masking may be done by software. A general interrupt inhibit may be applied if a signal is fed to the EI input of the encoder. If this is not requried, the EI input should be tied to ground. The priority of the incoming interrupts is determined in the priority encoder. If at least one interrupt request is active at the input of the encoder, an INTERRUPT signal is generated for the Interrupt Control (Figure 2-32). The code of the acti ve interrupt with the highest priority is clocked into the flip-flops of the 74175, coincident with the INTERRUPT ACKNOWLEDGE from Interrupt Control. 2-57
The outputs of the flip-flops are used as the three least significant bits of the Interrupt Vector to provide eight different start addresses for the interrupt routines. They are also decoded to form an acknowledge signal indicating which interrupt request has been served. In the handshake procedue this signal sets the acknowledge flip-flop (ACKN). The acknowledge flip-flop is reset only when the INTREQ signal is de-activated. With this logic, however, the INTREQ signal must be de-acti vated before the end of the interrupt routine (return instruction), otherwise, the routine may be repeated. 2-58
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8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4:
SIGNETICS ® reserves the right to
Page 5 and 6:
CONTENTS Chapter Page Preface .....
Page 7 and 8:
LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10:
FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12:
1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16:
In the area of development systems,
Page 17 and 18:
MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20:
The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71: the writing of I/O addresses is inh
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124:
PRODUCT DESCRIPTION Both the 8T31 a
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8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
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1 BII LATCHED ADDRESSABLE BIDIRECTI
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BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
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PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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