8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

More documents

Recommendations

Info

PRELIMINARY BIPOLAR LSI DIVISION CHANNEl 0 DBA DAB 0 0 FUNCTION Data transmission inhibited CHANEL1 0 1 Ai-Bi CHANNEL 2 1 0 Ai-Bi i Aj Bi Ai-Bi - CHANEL3 CHANNEl 4 i = Channel 0, 1,2,3,4,5,6, or 7 Aj - Bi = Data transmission from Ai to Bi Aj - Bj = Data transmission from Bi to Ai AS CHANNElS BS TRUTH TABLE FOR INTERNAL LATCHES CHANNELS LATCHES L1 L2 DIRECTION OF DATA CHANNEl 7 1 1 Monitoring state 1 0 Ai to Bi 0 1 Bj to Ai 0 0 No transmissjon Figure 1. Logic Diagram of 8X41 Asynchronous Bidirectional Bus Extender and Repeater INPUT /OUTPUT TRUTH TABLE EXTERNAL CONTROLS INPUT SIGNALS OUTPUT DRIVER SIGNALS DAB DBA AI BI ADI BDI H H L L H H H H L H H L H H H L L H H H H H H H H L L L H L H L L H H L H L H L H H H L H H H H L H L L L H L H L H H H L H H L L H NOTES L H H H H H Ai = External signal BDi = Output B driver L L X X H H ADi = Output A driver X = Don't care Bi = External signal 4 9!!110liC9
PRELIMINARY BIPOLAR LSI DIVISION DC CHARACTERISTICS vee = 5V (±5%); TA = ooe to 70 0 e LOAD CIRCUIT FOR OUTPUTS PARAMETER DESCRIPTION TEST CONDITIONS VOL *VB VIH (DBA, DAB only) VIL (DBA, DAB only) Vie Bus output low voltage (driver ON) Bus input threshold voltage (driver OFF~ High level input voltage Low level input voltage Input clamp voltage IOL = 70 rnA; Vee = Min Vee = Min; IlL = -18mA Min 1.3 2.0 Power ON / OFF VpD detector threshold 3.7 voltage IIH (DBA, High level input Vee = Max; DAB only) current VIN = 2.7V IlL (DBA, Low level input Vee = Max; DAB only) current VIN = O.4V II IOFF Bus input current (driver OFF) Bus leakage current (power OFF) Vee = Max; VB = 2.5V* Vee = Max; VB = OV* Vee = OV; VB = 2.5V* LIMITS Typ Vee = Max; lee Supply current AO-A7 = Low or 145 BO-B7 = Low and DBA = DAB = High Max UNITS 0.5 V vcc RI 60!! 1.7 V FROM OUTPUT O---+--_+_-.Q TEST UNDER TEST POINT V 0.8 V -1.5 V 4.35 V 20 J.l.A -0.4 rnA 100 -20 J.l.A 100 J.l.A 180 rnA R2 90n NOTE C L includes probe and jig capacitance *VB = VBUS CL 30pF AC CHARACTERISTICS Vee = 5V (±5%); TA = ooe to 70 0 e PARAMETER DESCRIPTION FROM TO tPLL tpHH tDHH tOLL Propagation delay Propagation delay Propagation delay Propagation delay Low Ai Low Bi High Ai High Bi High Ai High Bi Low Ai Low Bi Low BDi Low ADi High BDi High ADi High BDi High ADi Low BDi Low ADi tDEH Propagation delay Low DBA High ADi tDEL Propagation delay High DBA Low ADi tDEH Propagation delay Low DAB High BDi tDEL Propagation delay High DAB Low BDi tr Recovery time (see - - timing diagram) NOTES Ai = External signal ADi = Output A driver Bi = External signal BDi = Output B driver LIMITS TEST CONDITIONS Min Typ Max DBA = DAB = High 30 DBA = DAB = High 30 DBA = Low; DAB = High 25 DAB = Low; DBA = High 25 DBA = Low; DAB = High 25 DAB = Low; DBA = High 25 DAB = Low; Bi = Low 30 DAB = Low; Bi = Low 30 DBA = Low; Ai = Low 30 DBA = Low; Ai = Low 30 DBA = DAB = High 20 UNITS l1sec l1sec l1sec l1Sec l1Sec l1Sec l1Sec l1Sec l1Sec l1sec l1Sec G!!IIOliCG 5
Page 1 and 2:
8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4:
SIGNETICS ® reserves the right to
Page 5 and 6:
CONTENTS Chapter Page Preface .....
Page 7 and 8:
LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10:
FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12:
1.1 INTRODUCTION The Signetics 8X30
Page 13 and 14:
1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16:
In the area of development systems,
Page 17 and 18:
MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20:
The function of the operand fields
Page 21 and 22:
The Program Address logic data flow
Page 23 and 24:
1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26:
\- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28:
OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30:
The second, and most desirable, met
Page 31 and 32:
2.2 8X300 TIMING To understand the
Page 33 and 34:
XI ~~------------------------------
Page 35 and 36:
Table 2-3. 8X300 AC Electrical Char
Page 37 and 38:
2.2.2 Timing Calculations It is an
Page 39 and 40:
INSTRUCTION •••• tI INPUT I
Page 41 and 42:
Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44:
Normally, the instruction cycle tim
Page 45 and 46:
LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48:
Table 2-4. Bit Manipulation Functio
Page 49 and 50:
The following sections provide gene
Page 51 and 52:
6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54:
\Nhen interfacing program storage c
Page 55 and 56:
2.4.2 I/O Interface Typical interfa
Page 57 and 58:
The preceding descriptions should n
Page 59 and 60:
~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62:
stored in the successi ve-approxima
Page 63 and 64:
g) Priority logic - If more than on
Page 65 and 66:
~LK------------------------~ +S~ 1
Page 67 and 68:
2.5.2 Interrupt Control (Handshake)
Page 69 and 70:
The positive edge of the INTERRUPT
Page 71 and 72:
the writing of I/O addresses is inh
Page 73 and 74:
The outputs of the flip-flops are u
Page 75 and 76:
10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78:
BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80:
BIPOLAR LSI DIVISION phase. During
Page 81 and 82:
MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84:
MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86:
BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88:
111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139: = SABEl =---=========--__ F PRELIMI
Page 143 and 144: PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146: DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148: APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150: 8X300 INSTRUCTION SET S R/L 1314151
show all

8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?